Patents by Inventor Katsutoshi SUITO
Katsutoshi SUITO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735270Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.Type: GrantFiled: July 16, 2020Date of Patent: August 22, 2023Assignee: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
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Patent number: 11733879Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.Type: GrantFiled: October 14, 2022Date of Patent: August 22, 2023Assignee: Winbond Electronics Corp.Inventors: Oron Michael, Katsutoshi Suito
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Publication number: 20230035098Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.Type: ApplicationFiled: October 14, 2022Publication date: February 2, 2023Applicant: Winbond Electronics Corp.Inventors: Oron Michael, Katsutoshi Suito
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Publication number: 20220413748Abstract: A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.Type: ApplicationFiled: June 28, 2022Publication date: December 29, 2022Applicant: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito
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Patent number: 11507282Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.Type: GrantFiled: December 4, 2020Date of Patent: November 22, 2022Assignee: Winbond Electronics Corp.Inventors: Oron Michael, Katsutoshi Suito
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Publication number: 20220179562Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.Type: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Applicant: Winbond Electronics Corp.Inventors: Oron Michael, Katsutoshi Suito
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Patent number: 11315640Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).Type: GrantFiled: July 16, 2020Date of Patent: April 26, 2022Assignee: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
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Patent number: 10957415Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.Type: GrantFiled: May 19, 2017Date of Patent: March 23, 2021Assignee: Winbond Electronics Corp.Inventors: Kazuki Yamauchi, Katsutoshi Suito
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Publication number: 20210035647Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.Type: ApplicationFiled: July 16, 2020Publication date: February 4, 2021Applicant: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
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Publication number: 20210034304Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).Type: ApplicationFiled: July 16, 2020Publication date: February 4, 2021Applicant: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
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Patent number: 10783095Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.Type: GrantFiled: September 28, 2017Date of Patent: September 22, 2020Assignee: WINBOND ELECTRONICS CORP.Inventors: Takehiro Kaminaga, Katsutoshi Suito
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Patent number: 10641825Abstract: A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.Type: GrantFiled: October 8, 2018Date of Patent: May 5, 2020Assignee: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito
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Patent number: 10453524Abstract: A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory of the invention includes a memory cell array; a page reading element, which selects a page of the memory cell array and reads out data of the selected page to a page buffer/sense circuit; a page information storage element, which stores page information related to a range of a continuous reading; and a control element, which controls the continuous reading of the page. The control element determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.Type: GrantFiled: June 6, 2017Date of Patent: October 22, 2019Assignee: Winbond Electronics Corp.Inventors: Takehiro Kaminaga, Katsutoshi Suito
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Publication number: 20190227123Abstract: A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.Type: ApplicationFiled: October 8, 2018Publication date: July 25, 2019Applicant: Winbond Electronics Corp.Inventors: Makoto Senoo, Katsutoshi Suito
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Publication number: 20180090202Abstract: A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory 100 of the invention includes a memory cell array 110; a page reading element, which selects a page of the memory cell array 110 and reads out data of the selected page to a page buffer/sense circuit 180; a page information storage element 160, which stores page information related to a range of a continuous reading; and a control element 150, which controls the continuous reading of the page. The control element 150 determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.Type: ApplicationFiled: June 6, 2017Publication date: March 29, 2018Applicant: Winbond Electronics Corp.Inventors: Takehiro Kaminaga, Katsutoshi Suito
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Publication number: 20180088867Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.Type: ApplicationFiled: September 28, 2017Publication date: March 29, 2018Inventors: Takehiro KAMINAGA, Katsutoshi SUITO
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Publication number: 20180053568Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.Type: ApplicationFiled: May 19, 2017Publication date: February 22, 2018Applicant: Winbond Electronics Corp.Inventors: Kazuki Yamauchi, Katsutoshi Suito
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Patent number: 9870828Abstract: An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).Type: GrantFiled: September 27, 2016Date of Patent: January 16, 2018Assignee: Winbond Electronics Corp.Inventors: Katsutoshi Suito, Riichiro Shirota
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Publication number: 20170092368Abstract: An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).Type: ApplicationFiled: September 27, 2016Publication date: March 30, 2017Applicant: Winbond Electronics Corp.Inventors: Katsutoshi Suito, Riichiro Shirota
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Patent number: 9564236Abstract: The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ?V supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.Type: GrantFiled: October 7, 2015Date of Patent: February 7, 2017Assignee: Winbond Electronics Corp.Inventor: Katsutoshi Suito