Abstract: A portable information terminal such as mobile communication terminal having an earphone jack for sound input/output, PHS (personal handy-phone system), PDA (personal digital assistants), and mobile personal computer; a digital camera to connect to the portable information terminal, a digital camera connected portable terminal device comprising the portable information terminal and the digital camera, as well as to a method of controlling such a portable information terminal. The existing earphone jack provided on portable information terminals can be adopted as the plug for the digital camera or insertion plug for the connector of USB cable, so that the cost can be lowered and the system made compact to provide a highly flexible portable information terminal and a digital camera for use with the portable information terminal.

Abstract: An image processing apparatus which can effectively use a storage circuit provided together with a logic circuit, perform high speed processing, and reduce the power consumption without causing a decline in the performance. The image processing system includes a DRAM for storing image data and a logic circuit, which are provided together on a semiconductor chip. The DRAM is divided into a plurality of DRAM modules, and the divided plurality of DRAM modules are arranged around a logic circuit portion for carrying out graphic drawing processing etc. When the ratio of valid data occupying bit lines in one access increases, the distances from the DRAM modules to the logic circuit portion become uniform, the length of the longest path interconnection can be made shorter comparing with the case of arrangement fixed in one direction, and the overall operating speed can be improved.

Abstract: An encoder capable of making a processing time shorter, wherein the position of a first “1” bit seen from the MSB of digital data is output as a first bit encoded data and the second “1” bit is output as the second bit encoded data. A predetermined calculation is performed in parallel on the upper 8 bits of the digital data in the valid detector, the priority encoder, and the first valid bit mask unit, while a predetermined calculation is performed in parallel on the lower 8 bits in another priority encoder and another first valid bit mask unit.