Abstract: A method of data transfer applicable to processing elements which are interconnected by a network to form a multiprocessor system, whereby when a datum is to be transferred from a processing element to the network, the datum is sent to a transfer controller of the processing element at the same time that it is being read out from memory to be used by the processor of the processing element, or as it is being generated from the processor and written into memory. Thus, the system performance can be substantially improved, since the time required to execute each data transfer can be "hidden" within the processor execution time.

Abstract: A data transfer apparatus is capable of DMA-transferring the transferable data sequentially generated by a processor. In the data transfer apparatus is provided a counter or an address latch for storing data corresponding to the upper limit (or lower limit) of the address of the transferable data. The content of this counter or latch and the content of the DMA address counter are sequentially compared and transferred, and when these values finally become equal to each other and there is no longer new transferable data, the DMA transfer is stopped and a transfer request is retained. By this constitution, the data transfer between the processor and a device which requires the data generated by the processor may be done instantly and asynchronously.

Abstract: The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

Abstract: A FIFO memory using one of the ports of a RAM having two or more ports for writing and another port for reading is disclosed. Writing into the FIFO memory is done instantly, while reading from the FIFO memory is effected by holding the output of the preliminarily accessed RAM until the end of a reading operation. The output of the RAM is updated by a request from outside and according to the state of the FIFO memory, and this operation is done simultaneously with reading or writing.

Abstract: An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.

Abstract: A full adder is constituted with complementary MOS FETs, wherein delay time of adding time and carry signal delay time are shortened as a result of reduced number of stages of signal processing gates.