Patents by Inventor Katsuyuki Kimura
Katsuyuki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240160202Abstract: An information processing device is provided that includes an obtaining unit configured to obtain status data of a plurality of mechanisms in a processing step carried out in a production line, an abnormality detector configured to detect an abnormality based on the status data obtained by the obtaining unit, a surrogate model calculator configured to calculate a surrogate model based on the status data at time of detecting the abnormality, and an estimator configured to estimate an abnormality causal factor based on the surrogate model calculated earlier.Type: ApplicationFiled: October 24, 2023Publication date: May 16, 2024Applicant: OMRON CorporationInventors: Katsuyuki KIMURA, Shinsuke KAWANOUE
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Publication number: 20240045036Abstract: A signal processing device according to an embodiment includes input ends, first to Nth output ends, and a control circuit. The input ends respectively input signals. The first to Nth output ends are respectively associated with first to Nth groups (N is an integer of not less than two). Each of the first to Nth groups includes M (M is an integer of not less than two) consecutive input ends. The control circuit output, to the kth output end, a signal based on a signal obtained by adding signals respectively input to the M consecutive input ends of the kth group (k an integer of not less than 1 and not more than N). The control circuit switches combinations of input ends as the M input ends to set different combinations at the first setting to the Mth setting.Type: ApplicationFiled: February 16, 2023Publication date: February 8, 2024Inventors: Hiroshi KUBOTA, Nobu MATSUMOTO, Katsuyuki KIMURA
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Publication number: 20230296733Abstract: A LiDAR device according to an embodiment includes a rotating mirror having reflective surfaces, first/second light emitters each emitting light toward the rotating mirror, and first/second light receivers each receiving light reflected by the rotating mirror and converting the received light into an electrical signal. The first light emitter emits light in an orientation where an upper section of a distance measurement range is scanned. The second light emitter emits light in an orientation where a lower section of the distance measurement range is scanned. The first light receiver is provided at a position where light emitted by the first light emitter and reflected at the distance measurement range is received via the rotating mirror. The second light receiver is provided at a position where light emitted by the second light emitter and reflected at the distance measurement range is received via the rotating mirror.Type: ApplicationFiled: March 1, 2023Publication date: September 21, 2023Inventors: Masatoshi HIRONO, Hiroshi KUBOTA, Nobu MATSUMOTO, Katsuyuki KIMURA
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Publication number: 20230288543Abstract: According to the present embodiment, a light receiving device includes a plurality of pixels. Each of the pixels includes a photoelectric conversion element configured to be able to detect incidence of a photon and a power supply portion configured to change an applied voltage applied across both ends of the photoelectric conversion element.Type: ApplicationFiled: August 31, 2022Publication date: September 14, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi KUBOTA, Nobu MATSUMOTO, Katsuyuki KIMURA
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Patent number: 9253377Abstract: According to one embodiment, an image processing device includes a shift estimator, and a de-mosaic module. The shift estimator is configured to estimate a shift amount between a first pixel in a first image and a corresponding second pixel in a second image. The first image is taken by a first image pickup apparatus, and the second image is taken by a second image pickup apparatus. A focus position of the first image pickup apparatus is different from a focus position of the second image pickup apparatus. The de-mosaic module is configured to generate a first de-mosaic image by performing de-mosaic processing on each pixel in the first pixel using a pixel value of the corresponding second pixel, when the first pixel is determined to be in a state of in-focus based on the shift amount.Type: GrantFiled: February 13, 2013Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Hiwada, Katsuyuki Kimura, Tatsuya Mori
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Patent number: 8934736Abstract: According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image.Type: GrantFiled: August 11, 2011Date of Patent: January 13, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Katsuyuki Kimura
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Publication number: 20140285681Abstract: A multi-view imaging apparatus of an embodiment includes a plurality of imaging units each including an image sensor and a memory configured to store therein image data taken by the image sensor, the imaging units being daisy-chain connected to each other in order to send the image data, and also includes an interface unit connected to a lowermost imaging unit, the interface unit being configured to output pieces of image data taken by the plurality of imaging units to an outside. The imaging units each add own-stage data to data outputted from an upper-stage imaging unit, and output the resultant data to a lower-stage imaging unit.Type: ApplicationFiled: August 26, 2013Publication date: September 25, 2014Inventors: Kazuyo KANOU, Katsuyuki KIMURA, Yosuke BANDO, Kojiro SUZUKI, Hideho ARAKIDA, Fumihiko HYUGA, Kiwamu WATANABE, Hajime MATSUI, Atsushi MOCHIZUKI, Sho KODAMA, Akira MORIYA
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Patent number: 8730250Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.Type: GrantFiled: August 13, 2009Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Publication number: 20140009634Abstract: According to one embodiment, an image processing device includes a shift estimator, and a de-mosaic module. The shift estimator is configured to estimate a shift amount between a first pixel in a first image and a corresponding second pixel in a second image. The first image is taken by a first image pickup apparatus, and the second image is taken by a second image pickup apparatus. A focus position of the first image pickup apparatus is different from a focus position of the second image pickup apparatus. The de-mosaic module is configured to generate a first de-mosaic image by performing de-mosaic processing on each pixel in the first pixel using a pixel value of the corresponding second pixel, when the first pixel is determined to be in a state of in-focus based on the shift amount.Type: ApplicationFiled: February 13, 2013Publication date: January 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro HIWADA, Katsuyuki KIMURA, Tatsuya MORI
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Patent number: 8417063Abstract: According to one embodiment, an image processing apparatus connected to an external memory and a cache memory. The apparatus includes a counter, a coordinate calculator, a tag checker, a pixel referring module, a pixel value calculator and an outputting module. The counter determines a converted coordinate according to a predetermined execution sequence. The coordinate calculator calculates a unconverted coordinate used to calculate a converted pixel value located at the converted coordinate. The tag checker generates a conversion request to calculate the converted pixel value with reference to an unconverted pixel located at the unconverted coordinate. The pixel referring module reads the unconverted pixel from the cache memory based on the conversion request when the unconverted pixel is stored in the cache memory. The pixel value calculator calculates the converted pixel value with reference to the read unconverted pixel.Type: GrantFiled: March 21, 2011Date of Patent: April 9, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Yasukazu Okamoto, Tsuyoshi Nakano, Katsuyuki Kimura
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Patent number: 8413123Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.Type: GrantFiled: September 7, 2010Date of Patent: April 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Patent number: 8345113Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.Type: GrantFiled: July 30, 2009Date of Patent: January 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Keiri Nakanishi, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Masato Sumiyoshi, Yasuki Tanabe, Ryuji Hada
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Publication number: 20120288205Abstract: According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image.Type: ApplicationFiled: August 11, 2011Publication date: November 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuki TANABE, Takashi MIYAMORI, Katsuyuki KIMURA
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Publication number: 20120183207Abstract: According to one embodiment, an image processing apparatus connected to an external memory and a cache memory. The apparatus includes a counter, a coordinate calculator, a tag checker, a pixel referring module, a pixel value calculator and an outputting module. The counter determines a converted coordinate according to a predetermined execution sequence. The coordinate calculator calculates a unconverted coordinate used to calculate a converted pixel value located at the converted coordinate. The tag checker generates a conversion request to calculate the converted pixel value with reference to an unconverted pixel located at the unconverted coordinate. The pixel referring module reads the unconverted pixel from the cache memory based on the conversion request when the unconverted pixel is stored in the cache memory. The pixel value calculator calculates the converted pixel value with reference to the read unconverted pixel.Type: ApplicationFiled: March 21, 2011Publication date: July 19, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuki Tanabe, Takashi Miyamori, Yasukazu Okamoto, Tsuyoshi Nakano, Katsuyuki Kimura
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Patent number: 8176290Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.Type: GrantFiled: June 11, 2009Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takahisa Wada, Katsuyuki Kimura, Shunichi Ishiwata, Takashi Miyamori, Ryuji Hada, Keiri Nakanishi, Yasuki Tanabe, Masato Sumiyoshi
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Publication number: 20110138371Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.Type: ApplicationFiled: September 7, 2010Publication date: June 9, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasuki TANABE, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada
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Publication number: 20100229162Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.Type: ApplicationFiled: September 15, 2009Publication date: September 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryuji HADA, Takashi Miyamori, Keiri Nakanishi, Masato Sumiyoshi, Takahisa Wada, Yasuki Tanabe, Katsuyuki Kimura, Shunichi Ishiwata
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Publication number: 20100211758Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.Type: ApplicationFiled: December 29, 2009Publication date: August 19, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masato Sumiyoshi, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Yasuki Tanabe, Ryuji Hada
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Publication number: 20100110213Abstract: An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.Type: ApplicationFiled: September 2, 2009Publication date: May 6, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuyuki KIMURA, Takashi MIYAMORI, Shunichi ISHIWATA, Takahisa WADA, Keiri NAKANISHI, Masato SUMIYOSHI, Yasuki TANABE, Ryuji HADA
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Publication number: 20100110289Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.Type: ApplicationFiled: August 13, 2009Publication date: May 6, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasuki Tanabe, Takashi Miyamori, Shunichi Ishiwata, Katsuyuki Kimura, Takahisa Wada, Keiri Nakanishi, Masato Sumiyoshi, Ryuji Hada