Patents by Inventor Katsuyuki Nomura
Katsuyuki Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10649675Abstract: According to an embodiment, a storage controller comprises a circuitry configured to implement an address generator, a reader, and a duplication detector. The address generator is configured to generate a scan address indicating each storage area of a storage that stores therein externally written data, according to a particular scan pattern for defining an order of an address of data to be read. The reader is configured to read data from the storage area of the storage indicated by the scan address. The duplication detector is configured to detect whether the data read by the reader is a duplicate of any one of a past predetermined number of pieces of data.Type: GrantFiled: September 8, 2016Date of Patent: May 12, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoya Kodama, Takayuki Itoh, Katsuyuki Nomura
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Patent number: 10193579Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: GrantFiled: September 7, 2016Date of Patent: January 29, 2019Assignee: Toshiba Memory CorporationInventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
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Publication number: 20170228177Abstract: According to an embodiment, a storage controller comprises a circuitry configured to implement an address generator, a reader, and a duplication detector. The address generator is configured to generate a scan address indicating each storage area of a storage that stores therein externally written data, according to a particular scan pattern for defining an order of an address of data to be read. The reader is configured to read data from the storage area of the storage indicated by the scan address. The duplication detector is configured to detect whether the data read by the reader is a duplicate of any one of a past predetermined number of pieces of data.Type: ApplicationFiled: September 8, 2016Publication date: August 10, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tomoya KODAMA, Takayuki ITOH, Katsuyuki NOMURA
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Publication number: 20170070244Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: ApplicationFiled: September 7, 2016Publication date: March 9, 2017Inventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
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Publication number: 20130061088Abstract: An information storage device includes a semiconductor memory divided into storage regions and a management unit. The management unit manages the storage regions so that any storage region which caused read or write errors a predetermined threshold number of times, which may be two or more, is made unavailable for storing data.Type: ApplicationFiled: August 31, 2012Publication date: March 7, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuyuki Nomura
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Publication number: 20080080725Abstract: According to one embodiment, there is provided a sound mixing processing apparatus including: an input unit inputting N-channel (N?3) sound data and two-channel sound data; a mixing unit mixing the N-channel sound data and the two-channel sound data inputted from the input unit to output N-channel sound data produced by the mixing; and a down-mix processing unit obtaining two-channel sound data produced by down-mixing and gain-adjusted, from the N-channel sound data inputted from the mixing unit, to output the obtained sound data.Type: ApplicationFiled: September 28, 2007Publication date: April 3, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Takanobu Mukaide, Katsuyuki Nomura
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Publication number: 20080002952Abstract: According to one embodiment, a video reproducing apparatus processing video content data and reproducing a video signal from the video content data includes a storage device in which first display image data corresponding to a specific operation of a user is stored, an identification device identifying whether or not second display image data corresponding to a specific operation of the user is included in the video content data, and a reproducing processing device capable of performing first reproducing processing of reproducing a video signal in which the first display image data read from the storage device is blended, when it is identified by the identification device that the second display image data is included in the video content data.Type: ApplicationFiled: June 25, 2007Publication date: January 3, 2008Inventor: Katsuyuki Nomura
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Publication number: 20070147201Abstract: According to one embodiment of this invention, a first management information holding section holds first reproduction management information recorded on an optical disc and a second management information holding section holds second reproduction management information fetched from the exterior. A flag determining section determines whether a write end flag of the second reproduction management information is normal or not, a newest information determining section determines a newer one of the first and second reproduction management information items and a reproduction management information selecting section issues an instruction to reproduce the contents by use of the newer one of the reproduction management information items.Type: ApplicationFiled: December 6, 2006Publication date: June 28, 2007Inventor: Katsuyuki NOMURA
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Publication number: 20060129519Abstract: A signal output apparatus is provided comprising an input unit configured to receive a main data and a notice of the presence of any further information related to the main data, a notifying unit configured to notify the presence of the related information in response to the notice received from the input unit, an acquiring unit configured to acquire the related information in response to the notice received from the input unit, and an output unit configured to multiplex and output the related information acquired by the acquiring unit with the main data received by the input unit.Type: ApplicationFiled: November 28, 2005Publication date: June 15, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Sera, Katsuyuki Nomura
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Patent number: 6687784Abstract: A controller writes, after writing data into a nonvolatile memory unit, new management information that reflects the data wiring, into an area of the memory unit other than an area of the nonvolatile memory unit, which stores last management information. After that, the controller writes an old management information flag in relation to the last management information. Further, the controller searches the memory unit for updated, normal management information when initializing the memory system. If it does not find updated, normal management information, the controller restores updated management information on the basis of normal old management information related to the old management information flag.Type: GrantFiled: September 18, 2001Date of Patent: February 3, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Douniwa, Akihisa Fujimoto, Katsuyuki Nomura
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Patent number: 6601132Abstract: A rewritable nonvolatile memory comprises a block usage control table indicating a usage status of each block of the nonvolatile memory. When the data is written, it is determined whether or not the data is correctly written. If it is determined that the data is not correctly written, the block address is stored as a candidate address of a defective block and writing operation is performed for another block. If it is determined that the data is correctly written, the block usage control table is updated such that the usage status of the candidate of a defective block and the present block is changed to a used status.Type: GrantFiled: September 12, 2001Date of Patent: July 29, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Nomura, Akihisa Fujimoto
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Publication number: 20020069313Abstract: A controller writes, after writing data into a nonvolatile memory unit, new management information that reflects the data wiring, into an area of the memory unit other than an area of the nonvolatile memory unit, which stores last management information. After that, the controller writes an old management information flag in relation to the last management information. Further, the controller searches the memory unit for updated, normal management information when initializing the memory system. If it does not find updated, normal management information, the controller restores updated management information on the basis of normal old management information related to the old management information flag.Type: ApplicationFiled: September 18, 2001Publication date: June 6, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi Douniwa, Akihisa Fujimoto, Katsuyuki Nomura
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Patent number: 6377500Abstract: Logical block addresses are allocated to the blocks provided on a flash memory, respectively. Address translation tables (LTPb's) are provided on the flash memory, each for a group of blocks. Groups of logical block addresses are provided, each group for one group of blocks provided on the flash memory. The logical block addresses of each group have a specific field each. The same data item is contained in the specific fields of the logical block addresses of any group. The data item designates all blocks of the group corresponding to the group of the logical block addresses. Each table has a group of entries storing physical address information indicating the locations that the blocks take in the flash memory. At least one of the tables is stored on a RAM. When a logical address is given from a host system, a microprocessor determines whether a table corresponding to the logical address exists on the RAM. If such table does not exist, the table is copied from the flash memory to the RAM.Type: GrantFiled: November 9, 2000Date of Patent: April 23, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Akihisa Fujimoto, Katsuyuki Nomura
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Publication number: 20020039312Abstract: A rewritable nonvolatile memory comprises a block usage control table indicating a usage status of each block of the nonvolatile memory. When the data is written, it is determined whether or not the data is correctly written. If it is determined that the data is not correctly written, the block address is stored as a candidate address of a defective block and writing operation is performed for another block. If it is determined that the data is correctly written, the block usage control table is updated such that the usage status of the candidate of a defective block and the present block is changed to a used status.Type: ApplicationFiled: September 12, 2001Publication date: April 4, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuyuki Nomura, Akihisa Fujimoto