Patents by Inventor Katumi Ogiue

Katumi Ogiue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4111724
    Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.
    Type: Grant
    Filed: December 14, 1976
    Date of Patent: September 5, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Katumi Ogiue, Hiroyuki Kondo, Takashi Ishikawa, Takaaki Mori, Takahisa Nitta
  • Patent number: 4009484
    Abstract: A semiconductor device comprising monocrystalline semiconductor regions and a polycrystalline semiconductor region doped with gold and disposed between and adjacent to the monocrystalline regions. The high impedance appearing between the regions is utilized for isolating circuit elements which are formed in the monocrystalline regions.
    Type: Grant
    Filed: December 3, 1969
    Date of Patent: February 22, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Katumi Ogiue, Masaya Ohta, Shotaro Shibata
  • Patent number: RE31506
    Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.
    Type: Grant
    Filed: September 2, 1980
    Date of Patent: January 24, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Katumi Ogiue, Hiroyuki Kondo, Takashi Ishikawa, Takaaki Mori, Takahisa Nitta