Patents by Inventor Kaushik Barman
Kaushik Barman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230297824Abstract: A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear activation function from a memory. The PNL activation engine is capable of performing a polynomial approximation of the first non-linear activation function on the input data using the first set of coefficients. The PNL activation engine is capable of outputting a result from the polynomial approximation of the first non-linear activation function.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Xilinx, Inc.Inventors: Rajeev Patwari, Chaithanya Dudha, Jorn Tuyls, Kaushik Barman, Aaron Ng
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Patent number: 11113030Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.Type: GrantFiled: May 23, 2019Date of Patent: September 7, 2021Assignee: XILINX, INC.Inventors: Dinesh K. Monga, Shail Aditya Gupta, Samuel R. Bayliss, Kaushik Barman
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Patent number: 10623222Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.Type: GrantFiled: August 30, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Kaushik Barman, Parag Dighe, Baris Ozgul, Sneha Bhalchandra Date
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Publication number: 20200076660Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Applicant: Xilinx, Inc.Inventors: Kaushik Barman, Parag Dighe, Baris Ozgul, Sneha Bhalchandra Date
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Patent number: 9760146Abstract: Conditional activation and deactivation of a microprocessor. A hardware portion of an apparatus performs packet processing on received data, where the hardware portion selectively decodes the received data. A microprocessor performs data processing on decoded data, where the microprocessor is conditionally activated for performing the data processing and is conditionally deactivated when not performing the data processing. An output portion receives processed data and audibly renders the processed data without requiring the microprocessor.Type: GrantFiled: January 8, 2007Date of Patent: September 12, 2017Assignee: Imagination Technologies LimitedInventors: Luis Aldaz, Luis Aldaz, Sr., Kaushik Barman, Allan A. Johnson, Raghavendra Malladi
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Patent number: 9313078Abstract: A method relates generally to data transmission. In such a method, a peak detector detects a signal peak of an input signal exceeding a threshold amplitude. This detecting includes sampling the input signal at a sampling frequency to provide a sampled signal. The sampling frequency is in a range greater than a bandwidth frequency of a carrier signal used for providing the input signal and less than twice the bandwidth frequency. Samples of the sampled signal proximate to the signal peak are interpolated to provide a reconstructed peak. A cancellation pulse is applied by a cancellation pulse generator to the samples to reduce the signal peak. A version of the input signal is output after application of the cancellation pulse.Type: GrantFiled: April 9, 2015Date of Patent: April 12, 2016Assignee: XILINX, INC.Inventors: Kaushik Barman, Gregory C. Copeland
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Patent number: 9209988Abstract: A battery-powered WLAN communication device has an activity sensor operable to identify an available packet. A PHY module is awakened to begin receiving the packet. The PHY module decodes a full MAC address from a MAC portion of a header of the packet. A MAC address parser receives the MAC address and determines whether the packet is to be received by comparing the full MAC address to a MAC address of the WLAN communication device. The MAC address parser is awakened to perform the comparing and shutdown after. Packets to be received include beacon packets. A hardware centric MAC separate from the MAC address parser has a beacon processor capable of being awakened from a shutdown state to process a beacon packet. The PHY module, the MAC address parser, and the beacon processor module are operable to be awakened and shutdown independently of each other and of a microprocessor.Type: GrantFiled: August 2, 2012Date of Patent: December 8, 2015Assignee: Imagination Technologies LimitedInventors: Luis Aldaz, Jr., Luis Aldaz, Sr., Kaushik Barman, Allan A. Johnson, Raghavendra Malladi
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Patent number: 8924455Abstract: In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.Type: GrantFiled: February 25, 2011Date of Patent: December 30, 2014Assignee: Xilinx, Inc.Inventors: Kaushik Barman, Parag Dighe, Ragahavendar M. Rao
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Patent number: 8811251Abstract: An apparatus comprises a network physical layer and an activity sensor for sensing a packet and activating the network physical layer from shutdown. The network physical layer decodes a PHY header portion and a media access control header portion of a packet header. A MAC has a fixed hardware media access plane implementing IEEE 802.11 series MAC functionality and couples to a microprocessor. A MAC address parser receives the MAC header portion of the packet, for processing the MAC header portion of the packet, and for activating the MAC from a shutdown in response to recognizing a MAC address within the MAC header portion of the packet, such that the MAC is not activated if the MAC parser does not recognize the MAC address, wherein the MAC is operable, after activation, to perform MAC functionality without the microprocessor and to provide data from the packet to the microprocessor.Type: GrantFiled: August 1, 2012Date of Patent: August 19, 2014Assignee: Imagination Technologies, LimitedInventors: Allan A. Johnson, Raghavendra Malladi, Parag Ashok Dighe, Sriram Kankipati, Kaushik Barman, Luis Aldaz, Sr.
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Patent number: 8775496Abstract: Approaches for Cholesky decomposition of a matrix are described. A first circuit is configured to generate an inverse square root of an input value. A second circuit is configured to generate a product of a value output by the first circuit and provided at a first input and a value provided at a second input. A third circuit is configured to generate a difference between a value provided at the first input and a value provided at the second input of the third circuit. The first input of the third circuit is coupled to the output of the second circuit. A control circuit is configured to iteratively distribute a plurality of values of the matrix and the outputs of the first, second, and third circuits to the inputs of the first, second, and third circuits such that the Cholesky decomposition of the matrix is output by the third circuit.Type: GrantFiled: July 29, 2011Date of Patent: July 8, 2014Assignee: Xilinx, Inc.Inventors: Kaushik Barman, Raghavendar M. Rao
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Patent number: 8656260Abstract: Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a partial parity for each of multiple frames of the data block. The parallel combiner is coupled to the register and configured to generate a combination of bits from third bits and the second bits from the register. These third bits are iteratively those of the first bits within each of the frames of the data block. The circuit also includes respective exclusive-or circuits associated with the second bits. These exclusive-or circuits are coupled to the parallel combiner and the register. The respective exclusive-or circuit for each second bit is configured to generate the second bit from the combination of bits.Type: GrantFiled: July 29, 2011Date of Patent: February 18, 2014Assignee: Xilinx, Inc.Inventors: Kaushik Barman, Heramba Aligave, Sarvendra Govindammagari
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Publication number: 20130064234Abstract: An apparatus comprises a network physical layer and an activity sensor for sensing a packet and activating the network physical layer from shutdown. The network physical layer decodes a PHY header portion and a media access control header portion of a packet header. A MAC has a fixed hardware media access plane implementing IEEE 802.11 series MAC functionality and couples to a microprocessor. A MAC address parser receives the MAC header portion of the packet, for processing the MAC header portion of the packet, and for activating the MAC from a shutdown in response to recognizing a MAC address within the MAC header portion of the packet, such that the MAC is not activated if the MAC parser does not recognize the MAC address, wherein the MAC is operable, after activation, to perform MAC functionality without the microprocessor and to provide data from the packet to the microprocessor.Type: ApplicationFiled: August 1, 2012Publication date: March 14, 2013Applicant: HellosoftInventors: Kaushik Barman, Allan A. Johnson, Raghavendra Malladi, Sriram Kankipati, Parag Ashok Dighe, Luis Aldaz, SR.
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Publication number: 20130058267Abstract: A battery-powered WLAN communication device has an activity sensor operable to identify an available packet. A PHY module is awakened to begin receiving the packet. The PHY module decodes a full MAC address from a MAC portion of a header of the packet. A MAC address parser receives the MAC address and determines whether the packet is to be received by comparing the full MAC address to a MAC address of the WLAN communication device. The MAC address parser is awakened to perform the comparing and shutdown after. Packets to be received include beacon packets. A hardware centric MAC separate from the MAC address parser has a beacon processor capable of being awakened from a shutdown state to process a beacon packet. The PHY module, the MAC address parser, and the beacon processor module are operable to be awakened and shutdown independently of each other and of a microprocessor.Type: ApplicationFiled: August 2, 2012Publication date: March 7, 2013Applicant: HellosoftInventors: Kaushik Barman, Allan A. Johnson, Raghavendra Malladi, Luis Aldaz, SR.
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Patent number: 8243638Abstract: Passive listening in wireless communication. An activity sensor device senses a packet. A medium access control (MAC) address parser receives the packet, processes a header of the packet, and activates a MAC device in response to recognizing a MAC address within the header, such that the MAC device is not activated if the MAC address parser does not recognize the MAC address.Type: GrantFiled: January 8, 2007Date of Patent: August 14, 2012Assignee: Hellosoft, Inc.Inventors: Luis Aldaz, Luis Aldaz, Sr., legal representative, Kaushik Barman, Allan A. Johnson, Raghavendra Malladi, Sriram Kankipati, Parag Ashok Dighe
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Patent number: 8238278Abstract: Hardware-based beacon processing. A hardware-centric medium access control (MAC) device includes a packet receiver and a beacon processor. The packet receiver receives a plurality of packets comprising at least one beacon packet. The beacon processor receives packets of the plurality of packets and filters out unwanted packets of the plurality of packets without requiring the use of other components of the hardware-centric MAC device and without requiring the use of a microprocessor.Type: GrantFiled: January 8, 2007Date of Patent: August 7, 2012Assignee: Hellosoft, Inc.Inventors: Luis Aldaz, Luis Aldaz, Sr., legal representative, Kaushik Barman, Allan A. Johnson, Raghavendra Malladi
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Patent number: 8144727Abstract: A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is configured for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is configured for performing real-time data communication functions without requiring a microprocessor.Type: GrantFiled: August 3, 2010Date of Patent: March 27, 2012Assignee: HelloSoft, Inc.Inventors: Luis Aldaz, Luis Aldaz, Jr., legal representative, Kaushik Barman, Allan A. Johnson, Raghavendra Malladi
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Patent number: 8009773Abstract: A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of ā0sā and ā1sā in the MSBs.Type: GrantFiled: April 4, 2008Date of Patent: August 30, 2011Assignee: Hellosoft India Pvt. Ltd.Inventors: Sriram Kankipati, Kaushik Barman, Krushna Prasad Ojha
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Publication number: 20100309851Abstract: A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is configured for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is configured for performing real-time data communication functions without requiring a microprocessor.Type: ApplicationFiled: August 3, 2010Publication date: December 9, 2010Inventors: Luis ALDAZ, Kaushik BARMAN, Allan A. JOHNSON, Raghavendra MALLADI
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Patent number: 7792141Abstract: A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is for performing real-time data communication functions without requiring a microprocessor.Type: GrantFiled: January 8, 2007Date of Patent: September 7, 2010Assignee: HelloSoft, Inc.Inventors: Luis Aldaz, Luis Aldaz, Sr., legal representative, Kaushik Barman, Allan A. Johnson, Raghavendra Malladi
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Publication number: 20080165769Abstract: Hardware-based beacon processing. A hardware-centric medium access control (MAC) device includes a packet receiver and a beacon processor. The packet receiver receives a plurality of packets comprising at least one beacon packet. The beacon processor receives packets of the plurality of packets and filters out unwanted packets of the plurality of packets without requiring the use of other components of the hardware-centric MAC device and without requiring the use of a microprocessor.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Luis Aldaz, Kaushik Barman, Allan A. Johnson, Raghavendra Malladi