Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.

Abstract: Various embodiments of the present disclosure provide for centralized access permission management of a plurality of application instances.

Abstract: Various embodiments of the present disclosure provide for centralized access permission management of a plurality of application instances.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: This disclosure relates generally to method and system for providing assistance to interviewers. Technical interviewing is immensely important for enterprise but requires significant domain expertise and investment of time. The present disclosure aids assists interviewers with a framework via an interview assistant bot. The method initiates an interview session for a job description by selecting a set of qualified candidates resume to be interviewed. Further, the IA bot recommends each interviewer with a set of question and reference answer pairs prior initiating the interview. At each interview step, the IA bot records interview history and recommends interviewer with the revised set of questions. Further, an assessment score is determined for the candidate using the reference answer extracted from a resource corpus. Additionally, statistics about the interview process is generated, such as number and nature of questions asked, and its variation across to identify outliers for corrective actions.

Abstract: Provided herein, in certain embodiments, are compositions comprising an isolated heavy chain-hyaluronan/pentraxin 3 (“HC-HA/PTX3”) complex for use in methods of killing cancer cells. Also provided herein, are methods of inhibiting cancer cell regrowth of a tumor in an individual in need thereof, comprising contacting an area surrounding the tumor after a surgical procedure with an isolated HC-HA/PTX3 complex. Combinations and kits for use in practicing said methods also are provided herein.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: Various embodiments of the present disclosure provide for centralized access permission management of a plurality of application instances.

Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.

Abstract: A shortage of at least one resource is determined in a first radio network control entity that has joined a pool of radio network control resources. The first radio network control entity signals to at least one second radio network control entity of the pool a request for at least one resource. The at least one second radio network control entity receives the request for at least one resource and offers for the first radio network control entity.

Abstract: The present invention relates to identification of centromeric sequences of Candida dubliniensis and localization of CdCse4p centromeric histone to the identified region. Also the present invention relates to distinguishing Candida dubliniensis from other members of genus Candida.

Abstract: A shortage of at least one resource is determined in a first radio network control entity that has joined a pool of radio network control resources. The first radio network control entity signals to at least one second radio network control entity of the pool a request for at least one resource. The at least one second radio network control entity receives the request for at least one resource and offers for the first radio network control entity.

Abstract: This invention generally relates to immunogenic compositions that comprise an HIV RNA component and a HIV polypeptide component. Immunogenic compositions that deliver antigenic epitopes in two different forms—a first epitope from human immunodeficiency virus (HIV), in RNA-coded form; and a second epitope from HIV, in polypeptide form—are effective in inducing immune response to HIV. The invention also relates to a kit comprising an HIV RNA-based priming composition and an HIV polypeptide-based boosting composition. The kit may be used for sequential administration of the priming and the boosting compositions.

Abstract: The present invention relates to identification of centromeric sequences of Candida dubliniensis and localization of CdCse4p centromeric histone to the identified region. Also the present invention relates to distinguishing Candida dubliniensis from other members of genus Candida.

Abstract: A simultaneous ascending price auction (“SAA”) can be used to allocate advertising inventory to bidders. The advertising inventory can be, for example, radio or television advertisement spots (“spots”). The bidders can be advertisers that can provide advertisements for presentation in the spots. Two or more contiguous spots can define an advertising block. Spots or advertising blocks can be allocated to advertisers by the SAA mechanism based on bid criteria. The SAA can perform simultaneous advertisement scheduling and pricing. The auction allocation can be optimized to facilitate efficient allocation of advertisements to spots or blocks.

Abstract: A simultaneous ascending price auction (“SAA”) can be used to allocate advertising inventory to bidders. The advertising inventory can be, for example, radio or television advertisement spots (“spots”). The bidders can be advertisers that can provide advertisements for presentation in the spots. Two or more contiguous spots can define an advertising block. Spots or advertising blocks can be allocated to advertisers by the SAA mechanism based on bid criteria. The SAA can perform simultaneous advertisement scheduling and pricing. The auction allocation can be optimized to facilitate efficient allocation of advertisements to spots or blocks.

Abstract: A real-time collaborative design platform provides a hierarchical 3D model space as a plurality of nodes and branches. Each node may include at least one version of a sub-component and each version may include one or more attributes. The platform facilitates selecting a hierarchical tree from the 3D model space based, at least in part, upon at least one of the one or more attributes associated with sub-components. The platform also facilitates making the 3D model space accessible by multiple users over a network, such as the Internet. Also, each version of a sub-component is accessible in a library associated with the 3D model space.