Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.

Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.

Abstract: Radio receivers are known in the art. A conventional receiver requires external components for RF/image selectivity, IF selectivity and demodulation. Other solutions are, for example, a number of correction algorithms, which is an expensive solution. Instead, the “weak” image point is positioned at the side of the desired channel with the lowest unwanted RF signal strength. While this does not necessarily increase the actual image rejection, the perceived image rejection is clearly improved.

Abstract: An FM receiver includes control means for controlling the IF filter. The control means receive a first input signal in dependence of a received RF level signal and a second input signal in dependence of a demodulated signal and have an output coupled to the controllable IF filter.

Abstract: A tuner including an oscillator, a divider means for dividing the oscillator signal and a mixer, suitable for global tuner applications, i.e. U.S.A./Europe/Japan without any hardware change, the divider is switchable between at least two values.

Abstract: Receivers for receiving AM signals normally use many elements which are not integrable. This results in high costs and bulky circuits.

Abstract: Radio receivers are known in the art. A conventional receiver requires external components for RF/image selectivity, IF selectivity and demodulation. Other solutions are for example a number of correction algorithms, which is an expensive solution.

Abstract: In a tuning method, a commanded-tuning loop (CTL) tunes a receiver (REC) on the basis of a tuning command (TC) and a self-tuning loop (STL) tunes the receiver on the basis of a reception signal. To resolve a tuning conflict between the loops, one of the loops (CTL or STL) is calibrated (CAL) with respect to the other loop (STL or JKR CTL). Preferably, the commanded-tuning loop (CTL) is in an active state when the self-tuning loop (STL) is in-lock. This allows good reception under dynamic reception conditions.

Abstract: An RDS or RDBS radio broadcast receiver, utilizing a microcontroller and a serial communication bus, receives a list of alternative frequencies to allow the receiver to switch to an alternative frequency when the quality of the main radio broadcast signal deteriorates. Therefore the quality of the alternative frequency transmissions has to be updated from time to time. To avoid time delays caused by the relatively slow serial communication bus, the tuning section includes further controller for performing the alternative frequency updates.

Abstract: An FM receiver having an RF section, a first tunable mixer stage for the frequency conversion of a desired RF FM reception signal into a first intermediate frequency signal, an IF device and an FM demodulator. In order to enhance the integration of the apparatus, while maintaining a signal processing ability which is free from distortion, the FM receiver includes circuitry incorporated in the signal path for converting a single-phase signal into a pair of signals in mutual phase quadrature. The pair of phase-quadrature signals is applied to in-phase and quadrature signal paths of the IF device. The IF device having a polyphase IF filter incorporated in the in-phase and quadrature signal paths and has a bandpass characteristic which is symmetrical around its resonance frequency. The polyphase IF filter is coupled to the FM demodulator.

Abstract: Manually tunable analog receivers with AFC have the drawback that the AFC exhibits hysteresis and that in the event of fading pulling to an adjacent station may occur, whereas receivers with PLL electronic tuning have the drawbacks that tuning is comparatively slow and also inaccurate because of the tuning in discrete steps by a microprocessor. The present receiver combines the advantages of both analog manual tuning and electronic tuning. It includes two cooperating frequency loops, one loop (L1) being an AFC loop and the other loop (L2) having a frequency counter (13) for measuring the frequency (f.sub.0) of a tuning oscillator (6) which is controlled by both loops. Cooperation between the loops is provided by a control circuit (16) responsive to control signals supplied by both loops: an in-lock signal (in-1) and an in-window signal (in-w). Preferably, when the desired tuning is achieved, the power to a tuning section (12) of the receiver, forming part of the frequency loop (L2), is interrupted.

Abstract: An SSB pulse modulator which attenuates unwanted even harmonics of the carrier frequency without expensive filtering. The modulator comprises two pairs of comparators (12, 14 and 16, 18), and the sine and cosine components of the carrier signal are modulating signal [a(t)] and the Hilbert transform [a(t)] thereof are applied to respective ones of the comparators. EX-OR gates (20, 22) multiply together the outputs of each pair of comparators (12, 14 and (16, 18), the multiplied outputs being combined with each other in a signal combining arrangement (24). Each pair of the comparators produces the unwanted even harmonics, which are then attenuated by subtraction from each other in the combining arrangement.