Abstract: A signal processing apparatus includes a correlated double sampling unit and a processing unit. The correlated double sampling unit is arranged for receiving a reset signal and a data signal, obtaining a reset level and a first data level corresponding to the reset signal and the data signal, respectively, and outputting an output signal according to a level difference between the reset level and the first data level. The processing unit is coupled to the correlated double sampling unit, and is arranged for receiving a second data level of the data signal and a predetermined level, and comparing the second data level with the predetermined level to generate a detection result indicative of quality of the level difference.

Abstract: A pixel array comprises at least one long exposure pixel, short exposure pixel, and a control circuit. The long exposure pixel comprises a first photodiode to generate charges, a first image signal generating module for generating a first image sensing signal; and a first transfer switch device for passing the charges to the first image signal generating module via a first transfer control signal. The control circuit sets the first transfer control signal to be a first predetermined control voltage when the long exposure pixel is in an long exposure phase, and then sets the first transfer control signal to be a second predetermined control voltage when the short exposure pixel is in a short exposure phase.

Abstract: A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Abstract: A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: A correlated double sampling apparatus includes a first processing unit and a second processing unit. The first processing unit is arranged for receiving a reset signal, a data signal, and a predetermined signal; obtaining a reset level of the reset signal and a first data level of the data signal in a first operation mode; and obtaining a second data level of the data signal, and comparing the second data level with the predetermined signal to generate a detection result in a second operation mode. The second processing unit is arranged for storing the reset level and the first data level in the first operation mode, and selectively correcting an output signal according to the detection result in the second operation mode, wherein the output signal is determined according to a level difference between the reset level and the first data level.

Abstract: A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: In one embodiment the present invention includes an electrical arrangement comprising conductive elements such as electrical traces. The conductive elements carry differential signals. The conductive elements extend horizontally and have alternating sections around one or more center lines. Ground lines may be included the further enhance signal integrity. In one embodiment, magnetic field cancellation may be achieved by providing an offset between pairs of alternating differential elements.