Abstract: An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading.

Abstract: An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

Abstract: An embodiment is a method and apparatus to perform symbol synchronization. A sign element obtains signs of samples in a sample vector. A correlation estimator computes a correlation of the sample vector. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols prior to symbol synchronization detection. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

Abstract: An embodiment is a method and apparatus to process an input signal. An analog automatic gain control (AGC) processor controls an analog adjustable gain of the input signal using a feedback mechanism. The analog AGC processor generates a first signal. A processing circuit transforms the first signal into a second signal. A digital AGC processor controls a digital adjustable gain of the second signal using a feed-forward mechanism.

Abstract: An embodiment is a method and apparatus to perform symbol synchronization. A correlation estimator computes a correlation of a sample vector representative of a narrowband signal. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

Abstract: According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode, a second mod and a third mode. The interleaver performs repetitive encoding when placed in the second mode and even greater repetitive encoding when placed in the third mode.

Abstract: An embodiment is a method and apparatus to perform symbol synchronization. A sign element obtains signs of samples in a sample vector. A correlation estimator computes a correlation of the sample vector. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols prior to symbol synchronization detection. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

Abstract: An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. Another embodiment is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

Abstract: According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal over the power line. The spectral shaped module is adapted to compensate for amplitude distortion and further compensates for attenuations that will be realized during propagation of the transmitted signal over the power line.

Abstract: An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

Abstract: An embodiment is a method and apparatus to process an input signal. An analog automatic gain control (AGC) processor controls an analog adjustable gain of the input signal using a feedback mechanism. The analog AGC processor generates a first signal. A processing circuit transforms the first signal into a second signal. A digital AGC processor controls a digital adjustable gain of the second signal using a feed-forward mechanism.

Abstract: An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading.

Abstract: An embodiment is a method and apparatus to perform symbol synchronization. A correlation estimator computes a correlation of a sample vector representative of a narrowband signal. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

Abstract: An embodiment is a method and apparatus to cancel signal interference. A jammer remover removes an interfering signal from an input signal to generate a jammer-canceled signal using an adaptive filtering procedure. A jammer detector detects interference caused by the interfering signal.

Abstract: In one embodiment, an adapter is configured for coupling to a power line to receive and propagate multiple types of information including voice and video. In general, the adapter comprises (i) a physical layer adapter including a plug for coupling to the power line and logic to support electrical and mechanical connections to the power line, and (ii) logic to process information contained in HomePlug frames received over the physical layer and to route the processed information to one of a plurality of peripheral devices including a telephone, a monitor and a video recorder.

Abstract: The present invention provides a system and method to effectively suppress idle fax signals. In one embodiment, the method includes detecting a fax indicator signal. The method further includes calculating a short term energy of the fax indicator signal. The method also includes calculating a short term energy of fax data subsequent to the fax indicator signal. In addition, the method includes discarding the fax data when the short term energy of the fax data fails to exceed the short term energy of the fax indicator signal.

Abstract: In one embodiment, an adapter is configured for coupling to a power line to receive and propagate multiple types of information including voice and video. In general, the adapter comprises (i) a physical layer adapter including a plug for coupling to the power line and logic to support electrical and mechanical connections to the power line, and (ii) logic to process information contained in HomePlug frames received over the physical layer and to route the processed information to one of a plurality of peripheral devices including a telephone, a monitor and a video recorder.

Abstract: In one embodiment, a mechanism for multicast operations on a HomePlug frame, including voice information, that is being transmitted over a power line. Such multicasting is accomplished by placing a specified multicast address in a destination address field of the HomePlug frame. The specified multicast address corresponds to all adapters and a voice channel associated with a specific logical group.

Abstract: A method and apparatus to change compression methods without data loss. A real time system for converting compressing data using one of several compression methods is described. When a change in compression rates is requested, the system changes compression methods while continuing to compress data in real time without data loss.