Patents by Inventor Kaveh Shakeri
Kaveh Shakeri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9431124Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 20, 2015Date of Patent: August 30, 2016Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 9378821Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.Type: GrantFiled: March 8, 2013Date of Patent: June 28, 2016Assignee: Cypress Semiconductor CorporationInventors: Venkatraman Prabhakar, Long Hinh, Kaveh Shakeri, Sarath C. Puthenthermadam
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Publication number: 20150294731Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 20, 2015Publication date: October 15, 2015Inventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 8988938Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 17, 2014Date of Patent: March 24, 2015Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Patent number: 8897067Abstract: A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.Type: GrantFiled: March 12, 2013Date of Patent: November 25, 2014Assignee: Cypress Semiconductor CorporationInventors: Venkatraman Prabhakar, Kaveh Shakeri, Long T Hinh, Sarath C. Puthenthermadam
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Publication number: 20140301139Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 17, 2014Publication date: October 9, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Publication number: 20140264552Abstract: A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Venkatraman Prabhakar, Kaveh Shakeri, Long Hinh, Sarath C. Puthenthermadam
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Patent number: 8724386Abstract: A RECALL process in a memory circuit includes RECALLing the state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.Type: GrantFiled: June 18, 2013Date of Patent: May 13, 2014Assignee: Cypress Semiconductor CorporationInventors: Kaveh Shakeri, Jay Ashokkumar
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Patent number: 8675405Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: June 18, 2013Date of Patent: March 18, 2014Assignee: Cypress Semiconductor Corp.Inventors: Bogdan Georgescu, Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri
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Patent number: 8467243Abstract: A process of operating a memory circuit involves RECALLing a state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.Type: GrantFiled: September 23, 2010Date of Patent: June 18, 2013Assignee: Cypress Semiconductor CorporationInventors: Kaveh Shakeri, Jay Ashokkumar
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Patent number: 7859899Abstract: Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.Type: GrantFiled: March 28, 2008Date of Patent: December 28, 2010Assignee: Cypress Semiconductor CorporationInventors: Kaveh Shakeri, Kavin Jaejune Jang, Helmut Puchner
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Patent number: 7184461Abstract: One embodiment of the present invention includes a control circuit, an increment register, and an accumulator. The control circuit generates a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency. The channel enable signal selects a channel for a satellite in a global positioning system (GPS). The channel operates at a coarse/acquisition (C/A) clock signal having a second clock frequency. The increment register stores an increment value for the selected channel at the first clock signal. The accumulator generates a pseudo-random noise (PN) clock signal to a PN generator using the increment value.Type: GrantFiled: March 13, 2001Date of Patent: February 27, 2007Assignee: PRI Research & Development Corp.Inventors: Alireza Mehrnia, Kaveh Shakeri
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Patent number: 7173957Abstract: One embodiment of the present invention includes a first memory, an address counter, and an adder. The first memory having KN locations stores K sums of mixer samples during an epoch interval. The mixer samples are generated at a first clock frequency from a mixer for N channels corresponding to N satellites in a global positioning system (GPS) receiver. The address counter generates an address modulo-KN corresponding to a first location in the memory at the first clock frequency. The adder adds one of the mixer samples to contents of the first location to generate a sum. The sum is written into the first location.Type: GrantFiled: March 13, 2001Date of Patent: February 6, 2007Assignee: PRI Research & Development Corp.Inventors: Kaveh Shakeri, Alireza Mehrnia, Ali A. Eftekhar, Massoumeh Nassiri, Ali Fotowat-Ahmady
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Patent number: 6965631Abstract: One embodiment of the present invention includes a circular shift register, K storage elements, and a code register. The circular shift register having N data samples circularly shifts a first data sample of the N data samples into a data position at a first clock frequency. The N data samples correspond to signal received from one of K satellites in a global positioning system (GPS). The N data samples are loaded into the circular shift register at a second clock frequency. The K storage elements store K code sequences, respectively. Each of the K code sequences has N code samples and includes a first code sample being written at a code position corresponding to the data position at a third clock frequency. The K storage elements correspond to the K satellites. The code register stores the N code samples loaded from one of the K storage elements at a fourth clock frequency. The fourth clock frequency is K times faster than the first clock frequency.Type: GrantFiled: March 13, 2001Date of Patent: November 15, 2005Assignee: PRI Research & Development Corp.Inventors: Kaveh Shakeri, Alireza Mehrnia, Farshid Soheili-Najafabadi
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Patent number: 6839389Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.Type: GrantFiled: March 13, 2001Date of Patent: January 4, 2005Assignee: PRI Research & Development Corp.Inventors: Alireza Mehrnia, Kaveh Shakeri
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Publication number: 20030076154Abstract: Embodiments of the present invention provide systems and methods for reducing circuit power consumption by adjusting the supply voltage to the circuit. A preferred embodiment of such a method can be generally described as a method comprising the following steps: detecting a temperature change at the circuit; and adjusting a supply voltage to the circuit such that the power consumption is controlled. On the other hand, one embodiment of a system for reducing the power consumption of a circuit can be implemented with a device having structure for detecting a temperature change at the circuit and for adjusting a supply voltage to the circuit responsive to said temperature change at the circuit.Type: ApplicationFiled: October 17, 2002Publication date: April 24, 2003Inventors: Kaveh Shakeri, James D. Meindl
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Publication number: 20030076153Abstract: Embodiments of the present invention provide systems and methods for controlling circuit power consumption by adjusting the body voltage to the circuit. A preferred embodiment of such a method can be generally described as a method comprising the following steps: detecting a temperature change at the circuit; and adjusting a body voltage to a transistor in the circuit such that the power consumption is controlled. On the other hand, one embodiment of a system for controlling the power consumption of a circuit can be implemented with a device having structure for detecting a temperature change at the circuit and for adjusting a body voltage to the circuit responsive to said temperature change at the circuit.Type: ApplicationFiled: October 17, 2002Publication date: April 24, 2003Inventors: Kaveh Shakeri, James D. Meindl
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Publication number: 20020025006Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.Type: ApplicationFiled: March 13, 2001Publication date: February 28, 2002Inventors: Alireza Mehrnia, Kaveh Shakeri
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Publication number: 20020012387Abstract: One embodiment of the present invention includes a circular shift register, K storage elements, and a code register. The circular shift register having N data samples circularly shifts a first data sample of the N data samples into a data position at a first clock frequency. The N data samples correspond to signal received from one of K satellites in a global positioning system (GPS). The N data samples are loaded into the circular shift register at a second clock frequency. The K storage elements store K code sequences, respectively. Each of the K code sequences has N code samples and includes a first code sample being written at a code position corresponding to the data position at a third clock frequency. The K storage elements correspond to the K satellites. The code register stores the N code samples loaded from one of the K storage elements at a fourth clock frequency. The fourth clock frequency is K times faster than the first clock frequency.Type: ApplicationFiled: March 13, 2001Publication date: January 31, 2002Inventors: Kaveh Shakeri, Alireza Mehrnia, Farshid Soheili-Najafabadi
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Publication number: 20020009130Abstract: One embodiment of the present invention includes a first memory, an address counter, and an adder. The first memory having KN locations stores K sums of mixer samples during an epoch interval. The mixer samples are generated at a first clock frequency from a mixer for N channels corresponding to N satellites in a global positioning system (GPS) receiver. The address counter generates an address modulo-KN corresponding to a first location in the memory at the first clock frequency. The adder adds one of the mixer samples to contents of the first location to generate a sum. The sum is written into the first location.Type: ApplicationFiled: March 13, 2001Publication date: January 24, 2002Inventors: Kaveh Shakeri, Alireza Mehrnia, Ali A. Eftekhar, Massoumeh Nassiri, Ali Fotowat-Ahmady