Abstract: A system including an image data source and a transfer function module. The image data source is configured to provide image data. The transfer function module is configured to generate a transfer function to process the image data, define a first region of the transfer function, wherein a curvature of the transfer function in the first region is less than or equal to a threshold, define a second region of the transfer function, wherein a curvature of the transfer function in the second region is greater than the threshold, allocate a first number of sample inputs to the first region, allocate a second number of the sample inputs to the second region, wherein the second number is greater than the first number, map the sample inputs to sample outputs using the transfer function, and populate entries of a lookup table with the sample outputs.

Abstract: Transfer functions are often used for image processing. Look-up tables can be used to implement transfer functions in a processor-efficient manner. In one embodiment, the invention is an apparatus that includes a look-up table (LUT) storing sample outputs from an output range of a transfer function, the sample outputs corresponding to sample inputs from an input range of the transfer function, the sample inputs being distributed so that more sample inputs are associated with a first region of the transfer function than a second region of the transfer function; and an address module to calculate an index into the LUT based on image data. In one embodiment, the apparatus uses the LUT to process the image data.

Abstract: A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

Abstract: A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

Abstract: A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.