Patents by Inventor Kayoko Tajima

Kayoko Tajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7271612
    Abstract: A method for measuring the holding properties of a TFT array of an active matrix display panel comprising multiple pixel circuits with holding capacitors, this measuring method being characterized in that the multiple pixel circuits comprise at least a first pixel circuit and a second pixel circuit, and the method comprises a step for charging to the holding capacitor of the first pixel circuit, a step for then charging to the holding capacitor of the second pixel circuit, a step for performing an effect-eliminating procedure due to floating capacity, and a step for measuring the charge of the holding capacitor of the first and second pixel circuits wherein a predetermined holding time after charging has elapsed.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: September 18, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Takashi Miyamoto, Kayoko Tajima
  • Publication number: 20060109024
    Abstract: A method for measuring the holding properties of a TFT array of an active matrix display panel comprising multiple pixel circuits with holding capacitors, this measuring method being characterized in that the multiple pixel circuits comprise at least a first pixel circuit and a second pixel circuit, and the method comprises a step for charging to the holding capacitor of the first pixel circuit, a step for then charging to the holding capacitor of the second pixel circuit, a step for performing an effect-eliminating procedure due to floating capacity, and a step for measuring the charge of the holding capacitor of the first and second pixel circuits wherein a predetermined holding time after charging has elapsed.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 25, 2006
    Inventors: Takashi Miyamoto, Kayoko Tajima
  • Patent number: 7029934
    Abstract: A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a hold capacitor having a first electrode formed from the first structural material and a second electrode formed from the second structural material, where the testing method comprises a first step for applying a first voltage to the hold capacitor; a second step for applying a second voltage to the hold capacitor after the first step; a third step for measuring the charge in the pixel after applying the second voltage; and a fourth step for calculating the capacitance of the hold capacitor from the charge and the potential difference between the first voltage and the second voltage.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: April 18, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Kiyoshi Chikamatsu, Kayoko Tajima
  • Publication number: 20060046324
    Abstract: A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a hold capacitor having a first electrode formed from the first structural material and a second electrode formed from the second structural material, where the testing method comprises a first step for applying a first voltage to the hold capacitor; a second step for applying a second voltage to the hold capacitor after the first step; a third step for measuring the charge in the pixel after applying the second voltage; and a fourth step for calculating the capacitance of the hold capacitor from the charge and the potential difference between the first voltage and the second voltage.
    Type: Application
    Filed: July 7, 2005
    Publication date: March 2, 2006
    Inventors: Kiyoshi Chikamatsu, Kayoko Tajima
  • Publication number: 20060033447
    Abstract: A testing method for a TFT array substrate arranging pixels in a matrix where a pixel comprises a pixel selection transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a drive transistor having a gate formed from the first structural material and a source and a drain formed from the second structural material, wherein the testing method comprises: a first step for applying a first voltage to the drain of the pixel selection transistor and initializing the source voltage; a second step for applying a second voltage to the drain of the pixel selection transistor and measuring the current flowing between the drain and source of the pixel selection transistor; and a third step for determining the on-state resistance of the pixel selection transistor from the current and the potential difference between the first voltage and the second voltage.
    Type: Application
    Filed: July 1, 2005
    Publication date: February 16, 2006
    Inventors: Kiyoshi Chikamatsu, Kayoko Tajima
  • Publication number: 20050189960
    Abstract: A method for testing a thin film transistor array having pixels comprised of a transistor for controlling current, a capacitor connected between the gate terminal and the source terminal of this transistor, a first switch connected between the gate terminal and the drain terminal of this transistor, and a second switch, one terminal of which is connected to the drain terminal of this transistor and that turns on and off in synchronization with this first switch, this testing method characterized in that it comprises a step wherein the first and second switches are turned on, a step wherein a first voltage is applied to the other terminal of the second switch, and a step wherein a second voltage is applied to the other terminal of this second switch, and the charge flowing through this first switch is measured.
    Type: Application
    Filed: December 3, 2004
    Publication date: September 1, 2005
    Inventor: Kayoko Tajima
  • Publication number: 20050190169
    Abstract: A TFT array having pixels comprised of a transistor for controlling current, a capacitor connected between the gate terminal and the source terminal of this transistor, a first switch connected between the gate terminal and the drain terminal of this transistor, a first control line for controlling this first switch, a second switch, one terminal of which is connected to the drain terminal of this transistor, and a second control line for controlling this second switch.
    Type: Application
    Filed: December 3, 2004
    Publication date: September 1, 2005
    Inventor: Kayoko Tajima
  • Patent number: D631603
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: January 25, 2011
    Assignee: Shiseido Co., Ltd.
    Inventor: Kayoko Tajima
  • Patent number: D638164
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: May 17, 2011
    Assignee: Shiseido Co., Ltd.
    Inventor: Kayoko Tajima