Patents by Inventor Kazuaki Deguchi
Kazuaki Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962274Abstract: An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.Type: GrantFiled: August 13, 2021Date of Patent: April 16, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tsutomu Oonaro, Masamichi Tokuda, Makoto Tabei, Kazuaki Deguchi, Takayuki Kawano
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Patent number: 11316486Abstract: A high frequency circuit includes a transmit terminal and a transmit and receive terminal, a power amplifier that amplifies a high frequency signal inputted from the transmit terminal and outputs the high frequency signal toward the transmit and receive terminal, and an output matching circuit that is positioned on a signal path connecting the power amplifier and the transmit and receive terminal and that optimizes the output load impedance of the power amplifier. The output matching circuit includes a matching circuit coupled to an output terminal of the power amplifier, another matching circuit, and a switch that changes a connection between the matching circuits. The power amplifier and the switch are formed at a single semiconductor IC. The matching circuits are formed outside the semiconductor IC.Type: GrantFiled: April 24, 2020Date of Patent: April 26, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Kazuaki Deguchi
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Publication number: 20220069777Abstract: An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.Type: ApplicationFiled: August 13, 2021Publication date: March 3, 2022Inventors: Tsutomu OONARO, Masamichi TOKUDA, Makoto TABEI, Kazuaki DEGUCHI, Takayuki KAWANO
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Publication number: 20200343866Abstract: A high frequency circuit includes a transmit terminal and a transmit and receive terminal, a power amplifier that amplifies a high frequency signal inputted from the transmit terminal and outputs the high frequency signal toward the transmit and receive terminal, and an output matching circuit that is positioned on a signal path connecting the power amplifier and the transmit and receive terminal and that optimizes the output load impedance of the power amplifier. The output matching circuit includes a matching circuit coupled to an output terminal of the power amplifier, another matching circuit, and a switch that changes a connection between the matching circuits. The power amplifier and the switch are formed at a single semiconductor IC. The matching circuits are formed outside the semiconductor IC.Type: ApplicationFiled: April 24, 2020Publication date: October 29, 2020Inventor: Kazuaki DEGUCHI
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Patent number: 9349484Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.Type: GrantFiled: July 24, 2015Date of Patent: May 24, 2016Assignee: IMEC VZWInventors: Bob Verbruggen, Kazuaki Deguchi, Jan Craninckx
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Patent number: 9349727Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.Type: GrantFiled: January 15, 2015Date of Patent: May 24, 2016Assignee: Renesas Electronics CorporationInventors: Kazuaki Deguchi, Yasuo Morimoto, Masao Ito
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Publication number: 20160112058Abstract: A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.Type: ApplicationFiled: December 30, 2015Publication date: April 21, 2016Inventors: Kazuaki DEGUCHI, Masao ITO
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Patent number: 9258009Abstract: A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.Type: GrantFiled: October 17, 2012Date of Patent: February 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Deguchi, Masao Ito
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Publication number: 20160027528Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.Type: ApplicationFiled: July 24, 2015Publication date: January 28, 2016Applicant: IMEC VZWInventors: Bob Verbruggen, Kazuaki Deguchi, Jan Craninckx
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Patent number: 9166608Abstract: Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.Type: GrantFiled: June 5, 2015Date of Patent: October 20, 2015Assignee: IMEC VZWInventors: Kazuaki Deguchi, Bob Verbruggen, Jan Craninckx
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Publication number: 20150270846Abstract: A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.Type: ApplicationFiled: October 17, 2012Publication date: September 24, 2015Inventors: Kazuaki Deguchi, Masao Ito
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Publication number: 20150123207Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.Type: ApplicationFiled: January 15, 2015Publication date: May 7, 2015Inventors: Kazuaki Deguchi, Yasuo Morimoto, Masao Ito
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Patent number: 8957480Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.Type: GrantFiled: March 4, 2011Date of Patent: February 17, 2015Assignee: Renesas Electronics CorporationInventors: Kazuaki Deguchi, Yasuo Morimoto, Masao Ito
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Publication number: 20130334609Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.Type: ApplicationFiled: March 4, 2011Publication date: December 19, 2013Inventors: Kazuaki Deguchi, Yasuo Morimoto, Masao Ito
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Patent number: 7675363Abstract: PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.Type: GrantFiled: June 2, 2008Date of Patent: March 9, 2010Assignee: Renesas Technology Corp.Inventors: Kazuaki Deguchi, Takahiro Miki
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Publication number: 20080303592Abstract: PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.Type: ApplicationFiled: June 2, 2008Publication date: December 11, 2008Inventors: Kazuaki Deguchi, Takahiro Miki