Abstract: An integrated circuit including a random-access memory (RAM) macrocell is designed by the use of computer-aided tools that automatically generate a clock tree with minimal clock skew. The clock tree is then modified to delay the clock signal supplied to the RAM macrocell, to enable RAM set-up timing requirements to be satisfied. One preferred method modifies the clock tree by regenerating the clock tree, with a clock distribution cell on the RAM clock path redefined as a leaf cell. Another preferred method reduces the sizes of transistors in one or more clock distribution cells on the RAM clock path. These methods can usually provide an adequate RAM set-up timing margin while still permitting the entire clock tree to be generated automatically by the computer-aided tools.