Abstract: A DA converter has an N-bit binary counter which counts pulses of a predetermined frequency to generate a plurality of binary numbers within one conversion period. The binary counter supplies an output of lower n significant bits (n-1<N) to the upper (N-n+1)th to Nth bits of a comparator, and inverts an output of the upper (N-n) bits in order and supplies the inverted signal to the least significant bit to the (N-n)th bit of the comparator. The comparator sequentially compares digital data to be converted with the binary number output from the binary counter. The comparator then supplies the comparison results, pulses, to a low-pass filter. The low-pass filter converts a pulse train output by the comparator into a dc output.

Abstract: A semiconductor memory device provides redundancy using a decoder which examines a memory address and outputs the contents of memory at that address if the decoder determines that the address signal is selecting a correct bit cell in the memory, or clamps the output at a predetermined level if the decoder determines that the address signal is selecting an error bit cell in the memory.

Abstract: A semiconductor memory device is provided which includes a first transistor (TR1) having its emitter grounded, a second transistor (TR2) having its base and collector connected to the collector and base of the first transistor (TR1) and its emitter grounded, a data line (DL), and a third transistor (TR5) having its emitter-to-collector path connected between the data line (DL) and the base of the second transistor (TR2). The semiconductor memory device further includes a fourth transistor (TR6) having its base connected to another collector of the second transistor (TR2) and a fifth transistor (TR7) having its emitter-to-collector path connected between the base of the fourth transistor (TR6) and the row select line. Data is written through the data line (DL) and third transistor (TR5) and stored data is read out of the collector of the fourth transistor according to the conduction state of the second transistor (TR2).

Abstract: A phase comparison circuit comprises a phase difference signal producing circuit receiving a reference signal and variable frequency signal to produce a high level signal over a time period corresponding to the phase difference between both the signals, a discharge signal producing circuit for producing a high level signal a predetermined time after the high level signal of the phase difference signal producing circuit is completed, a first switching circuit connected in series with a capacitor and adapted to be closed in response to the high level signal from the phase difference signal producing circuit to enable the capacitor to be charged, a second switching circuit adapted to be closed in response to the high level signal from the discharge signal producing circuit to enable the capacitor to be discharged, a transistor having a base-to-emitter path connected to the capacitor, and a third switching circuit adapted to be closed in response to the variable frequency signal and ground the emitter of the tran