Abstract: An intake device for an internal combustion engine configures a flow passage for intake air that is drawn into combustion chambers. The intake device includes an intake manifold configuring multiple runners that respectively distribute intake air to multiple cylinders, a surge tank including a cavity that is connected to the runners and defines a convergence portion, a throttle body incorporating a throttle valve, and a connection pipe connecting the surge tank and the throttle body and configuring a curved flow passage extending between the throttle body and the surge tank. The connection pipe includes a partition plate that divides the curved flow passage into a circumferentially inner flow passage and a circumferentially outer flow passage.

Abstract: An intake device for an internal combustion engine configures a flow passage for intake air that is drawn into combustion chambers. The intake device includes an intake manifold configuring multiple runners that respectively distribute intake air to multiple cylinders, a surge tank including a cavity that is connected to the runners and defines a convergence portion, a throttle body incorporating a throttle valve, and a connection pipe connecting the surge tank and the throttle body and configuring a curved flow passage extending between the throttle body and the surge tank. The connection pipe includes a partition plate that divides the curved flow passage into a circumferentially inner flow passage and a circumferentially outer flow passage.

Abstract: Techniques are generally described for a converter including a PLL and a pulse deleting circuit. The pulse deleting circuit is configured to delete a pulse from one of the inputs to the PLL when a filtered output in the PLL falls below a first reference level and an unlocked state of the PLL is detected in response to a phase lag of one of the first and second pulse inputs with respect to the other. The pulse deleting circuit may also be configured to delete one pulse of the other of the first and second pulse inputs when the filtered output exceeds a second reference level and the unlocked state of the PLL is detected in response to a phase lead of the one of the first and second pulse inputs with respect to the other.

Abstract: Techniques are generally described for a converter including a PLL and a pulse deleting circuit. The pulse deleting circuit is configured to delete a pulse from one of the inputs to the PLL when a filtered output in the PLL falls below a first reference level and an unlocked state of the PLL is detected in response to a phase lag of one of the first and second pulse inputs with respect to the other. The pulse deleting circuit may also be configured to delete one pulse of the other of the first and second pulse inputs when the filtered output exceeds a second reference level and the unlocked state of the PLL is detected in response to a phase lead of the one of the first and second pulse inputs with respect to the other.

Abstract: A power failure detection circuit of a switching source includes: a switching element; a control circuit of the switching element, and a photocoupler. The phtocoupler includes a light emitting diode and a phototransistor. The light emitting diode is located at a primary side of a transformer and is serially connected to the control circuit. A cathode of the light emitting diode is connected to a capacitor. The phototransistor for detecting a power failure of an alternating current source is located at a secondary side of the transformer. A charging current flowing into the capacitor is used as a detection current for detecting the power failure of the alternate current source.

Abstract: A charge pump circuit of a switching source includes: a transformer; a rectifier diode of a secondary side of the transformer located at a ground side of a secondary winding wire; a capacitor for a charge pump; a power source of which a voltage is applied so as to charge accumulated in the capacitor; and a boosting transistor connected between the capacitor and the power source. A transformer voltage generated at a cathode side of the rectifier diode is at least partially used as a gate-driving voltage of the boosting transistor.

Abstract: A synchronous rectifying circuit for a flyback converter includes a synchronous rectifying element (Q2) coupled to the secondary winding (N2) of a transformer (T) and performing a synchronous rectifying operation according to an on/off operation of the synchronous rectifying element; an auxiliary inductance circuit (L3) coupled to the secondary winding (N2) of the transformer (T) and having an energy discharge time period shorter than that of the secondary winding (N2); and a control element (Q3) for turning the synchronous rectifying element (Q2) off in response to the detection of termination of the energy discharge of the auxiliary inductance circuit (L3).

Abstract: A synchronous rectifying circuit for a flyback converter includes a synchronous rectifying element (Q2) coupled to the secondary winding (N2) of a transformer (T) and performing a synchronous rectifying operation according to an on/off operation of the synchronous rectifying element; an auxiliary inductance circuit (L3) coupled to the secondary winding (N2) of the transformer (T) and having an energy discharge time period shorter than that of the secondary winding (N2); and a control element (Q3) for turning the synchronous rectifying element (Q2) off in response to the detection of termination of the energy discharge of the auxiliary inductance circuit (L3).

Abstract: A circuit element is produced in a circuit, and a thermoelectric cooling element comprising two dissimilar metals is thermally coupled to the circuit element for cooling the circuit element. A source is provided for applying a driving current to the circuit element. The circuit is arranged such that the driving current passes to the thermoelectric cooling element as an operating current thereof.

Abstract: A sum/differential signal processing circuit for use in a sound reproduction system, such as a Dolby surround processing system, includes a pair of operational amplifiers, a resistor connected between the inverting input terminals of the operational amplifiers, two resistors connected between the output terminals of the operational amplifiers, a signal output terminal connected to a junction between the two resistors for producing the sum of output signals from the output terminals of the operational amplifiers. A make switch is connected across one of the two resistors, which is selectively rendered ON and OFF. When the make switch is ON, the sum of output signals of the operational amplifiers is derived from the signal output terminal while when the make switch is OFF, the difference between the output signals thereof is derived therefrom. Even when a monaural signal is applied to each of the two signal input terminals, the signal is not cancelled by the circuit thus arranged.

Abstract: In a stereo sound field enlarging circuit, signals A and B applied to left and right input terminals are suitably processed so that signals A' and B' represented by the following equations are provided at respective left and right output terminals:A'=.vertline.A.vertline..sub.LPF +K(A-B)B'=.vertline.B.vertline..sub.LPF +K(B-A)where .vertline.A.vertline..sub.LPF (.vertline.B.vertline..sub.LPF) is the A (B) signal passed through a low-pass filter, and K is a constant.

Abstract: A voltage adder circuit for adding both balanced and unbalanced input signals. The balanced input signal is applied to respective transistors of a differential transistor pair, while the unbalanced input is applied to the emitter of an input transistor having a base-collector connected across the load of one side of the differential transistor pair. The output is taken from the load on the other side of the differential transistor pair, at the emitter of an output transistor having a base-collector coupled across the second load. The voltage adder at a circuit of the present invention may further be used in a low-distortion transistor circuit.

Abstract: An emitter-follower type single-ended push-pull circuit for which no temperature compensation is required and for which it is unnecessary to adjust the idle current. First and second complementary current mirror circuits are coupled as loads of respective first and second complementary differential amplifiers. Each of the differential amplifiers includes a first transistor to which an input signal voltage is applied, a second transistor to which a voltage at the output terminal of the circuit is applied as an input signal with the second transistor being connected in parallel with the first transistor, and a third transistor to which a voltage corresponding to an emitter or source voltage of a respective one of the output transistors is applied as an input voltage. The collector or drain output of the third transistor is employed as a drive output to a respective drive transistor in the output stage.

Abstract: An emitter-follower type SEPP circuit in which, by detecting idle currents and distortion components and feeding such signals back to an error amplifier in a real time mode, a very stable circuit with little crossover distortion is provided. The input signal is applied through opposite-polarity bias potential sources to noninverting first terminals of first and second error amplifiers, one for the positive half cycle and the other for the negative half cycle. The outputs of the two error amplifiers are applied through constant current sources to bases of respective bipolar transistors, the emitters of which are connected in a feedback arrangement to noninverting input terminals of the two amplifiers. The emitters of the two bipolar transistors are further connected through a resistance network to an output terminal. The resistance network also has a feedback terminal, which is connected through third and fourth bias potential sources to respective noninverting input terminals of the two amplifiers.

Abstract: An amplifier output circuit in which crossover distortion is largely eliminated, temperature compensation of idle current is obviated, and the idle current is maintained stable, independent of the magnitude of the input signal. In one embodiment in which two output amplifying elements are connected in a Class B SEPP circuit configuration, first and second error signal amplifiers are provided. While the first error amplifier functions as an error amplifier for an error voltage level shifted between the voltage at the output electrode of its current amplifying element and the voltage at the circuit input terminal, the second error amplifier functions as an error amplifier for an error voltage level shifted between the voltage at the output terminal of its amplifying element and the voltage at the circuit output terminal.

Abstract: A SEPP class B amplifier circuit of the non-cutoff type is improved by constructing the circuit such that the idle currents from first and second amplifiers are made independent of the circuit input by providing three-terminal error amplifiers in a feedback loop which receive, as inputs, level-shifted circuit inputs and output resistance network outputs, and amplifier outputs.

Abstract: A low noise power amplifier in which a buffer including a field effect transistor coupled in a source follower configuration is interposed between a voltage amplifying stage and a power amplifying stage, the latter utilizing a single-ended push-pull emitter follower configuration. A cascode transistor is cascade connected with the field effect transistor. A constant current source is provided for supplying current to the source of the field effect transistor. Field effect transistor buffers are preferably provided between the voltage amplifying stage and both positive and negative amplifying portions of the power amplifying stage.

Abstract: In an amplifier circuit having a first bipolar transistor receiving an input signal and coupled to the base of a second bipolar transistor of opposite conductivity, DC offset at the amplifier output is prevented by connecting a constant current source in parallel with the emitter resistor of the second transistor. DC feedback can be coupled from the amplifier output to the emitter of the second transistor and/or to a circuit component affecting the value of the input voltage at the base of the first transistor.

Abstract: An improved differential amplifier includes a pair of PNP transistors Q.sub.1 and Q.sub.2, in which an input signal on a signal input terminal IN is applied to the base of the transistor Q.sub.1. The base of an NPN transistor Q.sub.5 is connected to the base of the transistor Q.sub.1 to absorb the base current of the transistor Q.sub.1. A load circuit comprising a transistor Q.sub.6 and a variable resistor R.sub.5 is connected in series to the transistor Q.sub.5 and a current mirror circuit is coupled to the differential amplifier. The load circuit implements current mirror operation together with the current mirror circuit, whereby the input terminal voltage of the differential amplifier is maintained at substantially zero potential when no input signal is received irrespective of the variations of power source voltages.