Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; an amplifier that receives supply of the power supply voltage, and amplifies a signal based on the input signal; and a phase difference detector that detects a phase difference between the amplitude information of the input signal and the power supply voltage, wherein the first filter changes the first cutoff frequency in a direction in which the phase difference decreases.

Abstract: A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; an amplifier that receives supply of the power supply voltage, and amplifies a signal based on the input signal; and a phase difference detector that detects a phase difference between the amplitude information of the input signal and the power supply voltage, wherein the first filter changes the first cutoff frequency in a direction in which the phase difference decreases.

Abstract: The disclosed signal generator circuit has a four-phase signal generator circuit generating four-phase signals with a first frequency; an eight-phase signal generator circuit performing ½ frequency division of the four-phase signals to generate eight-phase signals with a second frequency; a first to a fourth harmonic rejection mixer circuits multiplying a first four-phase signal and a second four-phase signal of the four-phase signals by a first to a third eight-phase signals and a third to a fifth eight-phase signals of the eight-phase signals with mutually different combinations; a subtractor subtracting between outputs of the first and the fourth harmonic rejection mixer circuits to generate a first output signal with a third frequency; and an adder adding between outputs of the second and the third harmonic rejection mixer circuits to generate a second output signal with a third frequency whose phase is different from the first output signal by ?/2.

Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic that a gain of a frequency component lower than a second cutoff frequency is greater than a gain of a frequency component higher than the second cutoff frequency, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; and an amplifier that receives supply of the power supply voltage generated by the power supply circuit, and amplifies a signal based on the input signal.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: A power supply device includes a linear regulator including an output stage amplifier, a current sensing circuit, and a switching regulator. The current sensing circuit detects an output current of the linear regulator, and is disposed in parallel with the output stage amplifier, in a configuration corresponding to the output stage amplifier. The switching regulator operates in accordance with an output signal of the current sensing circuit. The linear regulator and the switching regulator operate in collaboration with each other to generate an output voltage at an output node.

Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic that a gain of a frequency component lower than a second cutoff frequency is greater than a gain of a frequency component higher than the second cutoff frequency, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; and an amplifier that receives supply of the power supply voltage generated by the power supply circuit, and amplifies a signal based on the input signal.

Abstract: A 4-phase filter includes four filter units including resistors and capacitors which inputs input signals, and provides the input signal via a switch buffer to a secondary capacitor provided in parallel to a primary capacitance of each filter unit, thus enabling a shift of an operational frequency band according to whether or not the switch buffer is in an output-high-impedance state.

Abstract: A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.

Abstract: A differential current source includes two source transistors, sources of which are respectively connected to a power source, and a mixer circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal and the second terminal being respectively connected to drains of the two source transistors, and the third terminal and the fourth terminal being respectively output terminals, wherein the mixer circuit changes a connection state in accordance with a local signal between a first connection state where the first terminal and the third terminal are connected and also the second terminal and the fourth terminal are connected, and a second connection state where the first terminal and the fourth terminal are connected and also the second terminal and the third terminal are connected.

Abstract: In order to suppress the enlargement of the circuit layout area of an LSI together with the cost, even at the time when the variation width of the filter characteristic is narrow within a wide range, a filter varies an element value of at least one kind of elements (3), which determine a filter characteristic of the filter circuit, according to an output of the sigma-delta modulator (1), which sigma-delta modulates a digital code input (Code), according to an operation clock (CLK), or according to a signal through a decoder (4), which performs a code-conversion to an output of the sigma-delta modulator (1).

Abstract: A frequency-variable filter has a GmC filter having a plurality of OTAs and a capacitor; and a pseudo-random value generator outputting pseudo-random value of which average value in a predetermined time corresponds to an input setting value. And at least an OTA for determining a cut-off frequency, out of the plurality of OTAs, is controlled so that transconductance thereof is variably-controlled according to the pseudo-random values, and the cut-off frequency is variably-controlled based on the input setting value.

Abstract: A filter circuit including first and second real filters of a zero-IF scheme. The first and second real filters receive an I component and a Q component separated from a reception signal, respectively; and a switch section for producing a complex filter by switchably connecting the first and second real filters through interconnection elements. The switch section further receiving a switching signal for connecting the first and second real filters, thereby switching from the zero-IF scheme to a low-IF scheme.

Abstract: A frequency-variable filter has a GmC filter having a plurality of OTAs and a capacitor; and a pseudo-random value generator outputting pseudo-random value of which average value in a predetermined time corresponds to an input setting value. And at least an OTA for determining a cut-off frequency, out of the plurality of OTAs, is controlled so that transconductance thereof is variably-controlled according to the pseudo-random values, and the cut-off frequency is variably-controlled based on the input setting value.

Abstract: A 4-phase filter includes four filter units including resistors and capacitors which inputs input signals, and provides the input signal via a switch buffer to a secondary capacitor provided in parallel to a primary capacitance of each filter unit, thus enabling a shift of an operational frequency band according to whether or not the switch buffer is in an output-high-impedance state.

Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.

Abstract: A noise cancellation circuit, which reduces noise in an output signal of an amplifier having an input resistance, a feedback resistance, and an operational amplifier, has: a first mixer circuit, which input an input signal across a first input terminal and a second input terminal of the operational amplifier, and performs frequency conversion of the input signal according to a first frequency signal; a noise cancellation amplifier, which amplifies an output signal of the first mixer circuit; a second mixer circuit, which performs frequency conversion of an output signal of the noise cancellation amplifier according to the first frequency signal; and a signal supply circuit, which supplies an output signal of the second mixer circuit to the first input terminal of the operational amplifier via an output resistance.

Abstract: In order to suppress the enlargement of the circuit layout area of an LSI together with the cost, even at the time when the variation width of the filter characteristic is narrow within a wide range, a filter varies an element value of at least one kind of elements (3), which determine a filter characteristic of the filter circuit, according to an output of the sigma-delta modulator (1), which sigma-delta modulates a digital code input (Code), according to an operation clock (CLK), or according to a signal through a decoder (4), which performs a code-conversion to an output of the sigma-delta modulator (1).