Patents by Inventor Kazuaki Sogawa
Kazuaki Sogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107200Abstract: A solid-state imaging device includes a pixel array that is quadrilateral and includes pixels arranged in rows and columns, where each of the pixels accumulates an electric charge resulting from photoelectric conversion. The pixel array includes: a first area including first pixels for obtaining a captured image; and a second area including a second pixel for individually identifying the solid-state imaging device. The second area is provided in the vicinity of at least one corner among four corners of the pixel array, where the vicinity is a range of a predetermined number of pixels away from the at least one corner. The second pixel includes circuit elements or optical elements different from circuit elements or optical elements in each of the first pixels.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Yoshihisa FUJIMORI, Yasuhiro KOSAKA, Takeshi SOWA, Kazuaki SOGAWA
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Publication number: 20120286835Abstract: A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as a digital value; a selector configured to select either the digital value or a fixed value; a digitally controlled oscillator configured to oscillate at a frequency corresponding to the value selected by the selector; and a control section configured to instruct the selector to select the fixed value until receiving a start signal, and after receiving the start signal, instruct the selector to select the digital value, and the frequency division section to start output, at timing of an edge of the reference clock signal.Type: ApplicationFiled: July 23, 2012Publication date: November 15, 2012Applicant: Panasonic CorporationInventors: Yuji Yamada, Masayoshi Kinoshita, Kazuaki Sogawa
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Patent number: 8106691Abstract: In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.Type: GrantFiled: August 9, 2011Date of Patent: January 31, 2012Assignee: Panasonic CorporationInventors: Kazuaki Sogawa, Masayoshi Kinoshita, Yuji Yamada
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Publication number: 20110291715Abstract: In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first 1/2 frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Kazuaki SOGAWA, Masayoshi KINOSHITA, Yuji YAMADA
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Patent number: 7978013Abstract: A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).Type: GrantFiled: October 25, 2006Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Shiro Dosho, Kazuaki Sogawa, Yuji Yamada, Naoshi Yanagisawa
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Patent number: 7920002Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.Type: GrantFiled: June 5, 2008Date of Patent: April 5, 2011Assignee: Panasonic CorporationInventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Akinori Matsumoto, Takashi Morie, Kazuaki Sogawa, Yukihiro Sasagawa, Masaya Sumita
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Publication number: 20110012664Abstract: A clock signal amplifier circuit includes: an inverter; a coupling capacitor connected to the input of the inverter; two resistors connected in series between the power supply potential and the ground potential, a connection node of the two resistors being connected to the input of the inverter; a feedback resistor provided between the input and output of the inverter; and two switches configured to perform a same open/close operation according to a control signal, the two switches being provided on any two of a supply path of the power supply potential to the inverter, a supply path of the ground potential to the inverter, and a feedback path of the inverter via the feedback resistor.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: PANASONIC CORPORATIONInventors: Masayoshi KINOSHITA, Kazuaki Sogawa, Yuji Yamada
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Patent number: 7808326Abstract: In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4.Type: GrantFiled: March 29, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventors: Kazuaki Sogawa, Masayoshi Kinoshita, Yuji Yamada, Junji Nakatsuka
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Publication number: 20100244878Abstract: In a PLL which does not include a loop filter, an additional circuit for subjecting a voltage-controlled oscillator to a burn-in test with an appropriate oscillation frequency is realized by a less circuit configuration. A gate terminal of a diode-connected transistor (13) which has the same polarity as a voltage-to-current conversion transistor (11) in a voltage-controlled oscillator (10) is connected to a gate terminal of the transistor (11) through a switch (12a), and a current supply (14) is connected to a drain terminal of the transistor (13). By appropriately controlling the current value supplied from the current supply (14) and the size ratio between the transistor (11) and the transistor (13), a current required for performing a burn-in test can be supplied to a ring oscillator in the voltage-controlled oscillator (10).Type: ApplicationFiled: December 20, 2007Publication date: September 30, 2010Inventors: Yuji Yamada, Masayoshi Kinoshita, Kazuaki Sogawa, Junji Nakatsuka
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Publication number: 20090295489Abstract: In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4.Type: ApplicationFiled: March 29, 2007Publication date: December 3, 2009Inventors: Kazuaki Sogawa, Masayoshi Kinoshita, Yuji Yamada, Junji Nakatsuka
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Publication number: 20090278614Abstract: A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).Type: ApplicationFiled: October 25, 2006Publication date: November 12, 2009Inventors: Shiro Dosho, Kazuaki Sogawa, Yuji Yamada, Naoshi Yanagisawa
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Publication number: 20080315933Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.Type: ApplicationFiled: June 5, 2008Publication date: December 25, 2008Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Akinori Matsumoto, Takashi Morie, Kazuaki Sogawa, Yukihiro Sasagawa, Masaya Sumita
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Patent number: 7323942Abstract: To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator 1 for comparing phases, and a frequency comparison loop having a frequency comparator 7 for comparing frequencies, wherein the frequency comparator 7 carries out frequency comparison using an input signal inputted from a calibration clock line CLcal 18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex 11, the reference clock signal being used for a phase comparator 1. Moreover, multiplication clock generators are configured using the dual loop PLL.Type: GrantFiled: December 30, 2005Date of Patent: January 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Ishizaka, Kazuaki Sogawa
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Patent number: 7298219Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.Type: GrantFiled: November 9, 2005Date of Patent: November 20, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Dosho, Takashi Morie, Kouji Okamoto, Yuji Yamada, Kazuaki Sogawa
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Publication number: 20060158259Abstract: To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator 1 for comparing phases, and a frequency comparison loop having a frequency comparator 7 for comparing frequencies, wherein the frequency comparator 7 carries out frequency comparison using an input signal inputted from a calibration clock line CLcal 18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex 11, the reference clock signal being used for a phase comparator 1. Moreover, multiplication clock generators are configured using the dual loop PLL.Type: ApplicationFiled: December 30, 2005Publication date: July 20, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Ishizaka, Kazuaki Sogawa
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Publication number: 20060139106Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.Type: ApplicationFiled: November 9, 2005Publication date: June 29, 2006Inventors: Shiro Dosho, Takashi Morie, Kouji Okamoto, Yuji Yamada, Kazuaki Sogawa
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Patent number: 7023284Abstract: In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.Type: GrantFiled: April 17, 2003Date of Patent: April 4, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuaki Sogawa, Ryoichi Suzuki
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Patent number: 6995607Abstract: In a low-pass filter, the filter characteristics equivalent to those of a conventional low-pass filter are maintained, the size of a capacitive element is decreased, and the low-pass filter operates stably. Further, a MOS capacitor is used as a capacitive element. For such purposes, in a low-pass filter including a first capacitive element, and a resistive element and a second capacitive element which are connected in series to the first capacitive element, a first electric current is supplied to the first input terminal connected to one end of the first capacitive element, and a second electric current is supplied to the second input terminal connected to the other end of the first capacitive element. Herein, the capacitance value of the first capacitive element is set according to the magnitude of the first electric current.Type: GrantFiled: March 15, 2004Date of Patent: February 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Dosho, Takashi Morie, Kazuaki Sogawa
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Publication number: 20040263261Abstract: In a low-pass filter, the filter characteristics equivalent to those of a conventional low-pass filter are maintained, the size of a capacitive element is decreased, and the low-pass filter operates stably. Further, a MOS capacitor is used as a capacitive element. For such purposes, in a low-pass filter including a first capacitive element, and a resistive element and a second capacitive element which are connected in series to the first capacitive element, a first electric current is supplied to the first input terminal connected to one end of the first capacitive element, and a second electric current is supplied to the second input terminal connected to the other end of the first capacitive element. Herein, the capacitance value of the first capacitive element is set according to the magnitude of the first electric current.Type: ApplicationFiled: March 15, 2004Publication date: December 30, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shiro Dosho, Takashi Morie, Kazuaki Sogawa
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Publication number: 20040196107Abstract: In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.Type: ApplicationFiled: February 5, 2004Publication date: October 7, 2004Inventors: Kazuaki Sogawa, Ryoichi Suzuki