Patents by Inventor Kazuaki Takai

Kazuaki Takai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164936
    Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 2, 2021
    Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
    Inventors: Youichi Okita, Wensheng Wang, Kazuaki Takai
  • Publication number: 20200251551
    Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
    Type: Application
    Filed: January 3, 2020
    Publication date: August 6, 2020
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Youichi Okita, Wensheng Wang, Kazuaki Takai
  • Patent number: 8652854
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 8542041
    Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: September 24, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mitsuhiro Ogai, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
  • Publication number: 20120171785
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 8153448
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Publication number: 20100253419
    Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Mitsuhiro OGAI, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
  • Publication number: 20090280577
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tomohiro TAKAMATSU, Junichi WATANABE, Ko NAKAMURA, Wensheng WANG, Naoyuki SATO, Aki DOTE, Kenji NOMURA, Yoshimasa HORII, Masaki KURASAWA, Kazuaki TAKAI
  • Patent number: 7547933
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: June 16, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Publication number: 20080160645
    Abstract: After bottom electrode film is formed, a first ferroelectric film is formed thereon. Then, the first ferroelectric film is allowed to crystallize. Thereafter, a second ferroelectric film is formed on the first ferroelectric film. Next, a top electrode film is formed on the second ferroelectric film, and the second ferroelectric film is allowed to crystallize.
    Type: Application
    Filed: February 6, 2008
    Publication date: July 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Ko Nakamura, Kazuaki Takai
  • Patent number: 7247504
    Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Fujitsu Limited
    Inventors: Osamu Matsuura, Kenji Maruyama, Kazuaki Takai
  • Patent number: 7176132
    Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: February 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Naoya Sashida, Katsuyoshi Matsuura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 7029984
    Abstract: A method is disclosed for fabricating a semiconductor device having a memory employing a ferroelectric capacitor in which the orientation of the ferroelectric film is controlled. The method for fabricating the semiconductor device includes a first film deposition process for forming a first ferroelectric layer, and a second film deposition process for forming a second ferroelectric layer on the first ferroelectric layer. The film deposition temperature of the first film deposition process is set to at least 600° C.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: April 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Horii, Masaaki Nakabayashi, Masaki Kurasawa, Kou Nakamura, Kazuaki Takai, Hideyuki Noshiro, Shigeyoshi Umemiya
  • Publication number: 20050242381
    Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.
    Type: Application
    Filed: December 30, 2004
    Publication date: November 3, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Matsuura, Kenji Maruyama, Kazuaki Takai
  • Publication number: 20050215006
    Abstract: A method is disclosed for fabricating a semiconductor device having a memory employing a ferroelectric capacitor in which the orientation of the ferroelectric film is controlled. The method for fabricating the semiconductor device includes a first film deposition process for forming a first ferroelectric layer, and a second film deposition process for forming a second ferroelectric layer on the first ferroelectric layer. The film deposition temperature of the first film deposition process is set to at least 600° C.
    Type: Application
    Filed: May 25, 2005
    Publication date: September 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Yoshimasa Horii, Masaaki Nakabayashi, Masaki Kurasawa, Kou Nakamura, Kazuaki Takai, Hideyuki Noshiro, Shigeyoshi Umemiya
  • Publication number: 20050161717
    Abstract: After bottom electrode film is formed, a first ferroelectric film is formed thereon. Then, the first ferroelectric film is allowed to crystallize. Thereafter, a second ferroelectric film is formed on the first ferroelectric film. Next, a top electrode film is formed on the second ferroelectric film, and the second ferroelectric film is allowed to crystallize.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 28, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Ko Nakamura, Kazuaki Takai
  • Patent number: 6855974
    Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: February 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Osamu Matsuura, Kenji Maruyama, Kazuaki Takai
  • Patent number: 6812510
    Abstract: A ferroelectric capacitor having a ferroelectric layer and a pair of electrodes, in which the ferroelectric layer contains carbon or carbon atoms of 5×1018 cm−3 or less, and the pair of electrodes is formed by a MOCVD (Metal Organic Chemical Vapor Deposition) method. A process for manufacturing a ferroelectric capacitor having the steps of forming a ferroelectric layer on one of a pair of electrodes; heating the layer at a temperature higher than when forming the layer, and to form the other electrode on the ferroelectric layer, or the steps of forming a ferroelectric layer on one of a pair of electrodes; forming the other electrode on the ferroelectric layer; and heating the layer at a temperature higher than when forming the layer to form the other electrode on the ferroelectric layer, to control carbon atoms of the ferroelectric layer to be 5×1018 cm−3 or less.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: November 2, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Horii, Osamu Matsuura, Katsuyoshi Matsuura, Kazuaki Takai
  • Publication number: 20040166596
    Abstract: There are provided a step of forming an insulating film over a semiconductor substrate, a step of exciting a plasma of a gas having a molecular structure in which hydrogen and nitrogen are bonded and then irradiating the plasma onto the insulating film, a step of forming a self-orientation layer made of substance having a self-orientation characteristic on the insulating film, and a step of forming a first conductive film made of conductive substance having the self-orientation characteristic on the self-orientation layer.
    Type: Application
    Filed: October 29, 2003
    Publication date: August 26, 2004
    Inventors: Naoya Sashida, Katsuyoshi Matsuura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Publication number: 20040135183
    Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 15, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Matsuura, Kenji Maruyama, Kazuaki Takai