Patents by Inventor Kazuaki TAKESHIGE

Kazuaki TAKESHIGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10528384
    Abstract: An information processing apparatus includes a memory; and a processor. The processor is configured to execute partitioning a predetermined matrix whose values of elements are to be generated by a matrix operation, into a predetermined number of first submatrices whose dimension in at least one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers used for the matrix operation, and into the predetermined number of second submatrices that are different from the predetermined number of the first submatrices; and assigning a matrix operation to generate values of elements of each of the predetermined number of the first submatrices, and a matrix operation to generate values of elements of each of the predetermined number of the second submatrices, to each of the predetermined number of threads.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kazuaki Takeshige
  • Patent number: 10417302
    Abstract: A parallel LU-factorization method executed in a parallel computer including a plurality of processing nodes which execute LU-factorization in parallel, the method causes each of the plurality of processing nodes to execute processing of; measuring a first time period, which is a time period from when a matrix product for a matrix of a first size is completed to when communication with a different processing node out of the plurality of processing nodes is completed; and altering a size of a matrix to be used for a matrix product to a second size smaller than the first size in a case where the measured first time period is equal to or longer than a predetermined time period.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 17, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kazuaki Takeshige
  • Publication number: 20180341517
    Abstract: An information processing apparatus includes a memory; and a processor. The processor is configured to execute partitioning a predetermined matrix whose values of elements are to be generated by a matrix operation, into a predetermined number of first submatrices whose dimension in at least one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers used for the matrix operation, and into the predetermined number of second submatrices that are different from the predetermined number of the first submatrices; and assigning a matrix operation to generate values of elements of each of the predetermined number of the first submatrices, and a matrix operation to generate values of elements of each of the predetermined number of the second submatrices, to each of the predetermined number of threads.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 29, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kazuaki TAKESHIGE
  • Patent number: 10013393
    Abstract: A parallel computer system including a plurality of processors configured to perform LU factorization in parallel, the system is configured to cause each of the plurality of processors to execute processing including: generating a first panel by integrating a plurality of row panels among panels of a matrix to be subjected to the LU-factorization, the plurality of row panels being processed by the processor, generating a second panel by integrating a plurality of column panels among the panels of the matrix, the plurality of column panels being processed by the processor, and computing a matrix product of the first panel and the second panel. In parallel with the computation of the matrix product, each processor is configured to receive or transmit a column panel to be used for computation of a subsequent matrix product from or to another processor among the plurality of processors.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 3, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kazuaki Takeshige
  • Publication number: 20170242826
    Abstract: A parallel LU-factorization method executed in a parallel computer including a plurality of processing nodes which execute LU-factorization in parallel, the method causes each of the plurality of processing nodes to execute processing of; measuring a first time period, which is a time period from when a matrix product for a matrix of a first size is completed to when communication with a different processing node out of the plurality of processing nodes is completed; and altering a size of a matrix to be used for a matrix product to a second size smaller than the first size in a case where the measured first time period is equal to or longer than a predetermined time period.
    Type: Application
    Filed: November 28, 2016
    Publication date: August 24, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Kazuaki TAKESHIGE
  • Publication number: 20160357707
    Abstract: A parallel computer system including a plurality of processors configured to perform LU factorization in parallel, the system is configured to cause each of the plurality of processors to execute processing including: generating a first panel by integrating a plurality of row panels among panels of a matrix to be subjected to the LU-factorization, the plurality of row panels being processed by the processor, generating a second panel by integrating a plurality of column panels among the panels of the matrix, the plurality of column panels being processed by the processor, and computing a matrix product of the first panel and the second panel. In parallel with the computation of the matrix product, each processor is configured to receive or transmit a column panel to be used for computation of a subsequent matrix product from or to another processor among the plurality of processors.
    Type: Application
    Filed: April 25, 2016
    Publication date: December 8, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Kazuaki TAKESHIGE