Abstract: A mounting structure of a semiconductor device is configured by connecting (i) a first protruding electrode [a bump (A5)] formed on a first electronic component [a substrate (2) or a semiconductor element (A1)] and (ii) a second protruding electrode [a bump (B6)] formed on a second electronic component [a semiconductor element (B11)]. The first protruding electrode and the second protruding electrodes are made of different metal materials. The first protruding electrode is harder than the second protruding electrode, has a pointed end, and is embedded in the second protruding electrode.

Abstract: A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.

Abstract: Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.

Abstract: A solar battery module substrate includes an insulating substrate on which a conductive pattern and an insulating protective film are formed, the conductive pattern including: cathode mounting terminals each of which is to be connected with a cathode of a solar battery cell; anode mounting terminals each of which is to be connected with an anode of the solar battery cell; and first module wiring, the first module wiring connecting a cathode mounting terminal to be connected with a cathode of one solar battery cell with an anode mounting terminal to be connected with an anode of another solar battery cell connected in series with said one solar battery cell, the insulating protective film having at least one opening for exposing the cathode mounting terminal and the anode mounting terminal, and the opening being positioned inside a portion of the solar battery module substrate on which portion the solar battery cell is to be projected.

Abstract: A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.

Abstract: Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.

Abstract: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.

Abstract: A method of multi-layer welding in which the welding operation is performed according to a path of welding defined by interpolating a plurality of instructed points by a suitable line, the method being characterized by storing in a memory device the coordinates actually passed by a welding torch in the welding operation of the first layer at the instructed points and determining the welding path of the second and succeeding layers by adding a predetermined amount of shift to the actual detected coordinates stored in the memory device at the instructed points and interpolating the shifted coordinates by a suitable line.