Patents by Inventor Kazufumi Shiozawa
Kazufumi Shiozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11526975Abstract: According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.Type: GrantFiled: September 4, 2019Date of Patent: December 13, 2022Assignee: KIOXIA CORPORATIONInventors: Yuki Watanabe, Taiki Kimura, Kazufumi Shiozawa, Kouichi Nakayama
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Publication number: 20200118261Abstract: According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.Type: ApplicationFiled: September 4, 2019Publication date: April 16, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuki WATANABE, Taiki KIMURA, Kazufumi SHIOZAWA, Kouichi NAKAYAMA
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Patent number: 9760017Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.Type: GrantFiled: July 20, 2015Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazufumi Shiozawa, Toshihide Kawachi, Masamichi Kishimoto, Nobuhiro Komine, Yoshimitsu Kato
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Publication number: 20160274470Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.Type: ApplicationFiled: July 20, 2015Publication date: September 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazufumi SHIOZAWA, Toshihide KAWACHI, Masamichi KISHIMOTO, Nobuhiro KOMINE, Yoshimitsu KATO
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Patent number: 9368413Abstract: According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure amount in the light exposure are estimated based on a brightness value of the pattern under each of the optical conditions.Type: GrantFiled: September 11, 2014Date of Patent: June 14, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhiro Komine, Yoshimitsu Kato, Kazufumi Shiozawa
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Publication number: 20160005661Abstract: According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure amount in the light exposure are estimated based on a brightness value of the pattern under each of the optical conditions.Type: ApplicationFiled: September 11, 2014Publication date: January 7, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Nobuhiro KOMINE, Yoshimitsu KATO, Kazufumi SHIOZAWA
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Publication number: 20150253680Abstract: A method of calculating the amount of aberration is provided according to an embodiment. In the method of calculating the amount of aberration, a simulation is performed to calculate for each Zernike term the aberration sensitivity of an aberration that is generated on a substrate when a lithography tool performs exposure processing on the substrate by using a mask on which a mask pattern is formed. A substrate pattern corresponding to the mask pattern is formed on the substrate by using the lithography tool. The amount of misalignment of the substrate pattern is then measured. Moreover, the amount of aberration for each Zernike term is calculated on the basis of the aberration sensitivity and the amount of misalignment.Type: ApplicationFiled: September 11, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kazufumi Shiozawa, Sayaka Tamaoki
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Patent number: 8759929Abstract: A solid-state imaging device includes: a substrate including a plurality of light receiving sections; and a color filter including a guided-mode resonant grating provided immediately above each of the plurality of light receiving sections, at least one of an upper surface and a lower surface of the guided-mode resonant grating being covered with a layer having a lower refractive index than the guided-mode resonant grating.Type: GrantFiled: March 18, 2010Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazufumi Shiozawa, Yusaku Konno, Naotada Okada
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Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
Patent number: 8546178Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a translucent electrode. The substrate includes a first region provided along periphery of a first major surface and a second region provided on center side of the first major surface as viewed from the first region. The first semiconductor layer is provided on the first major surface of the substrate. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting layer. The translucent electrode is provided on the second semiconductor layer. A reflectance in the second region is higher than a reflectance in the first region.Type: GrantFiled: July 12, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Morioka, Takayoshi Fujii, Toshitake Kitagawa, Kazufumi Shiozawa, Taisuke Sato, Hidefumi Yasuda, Yuko Kato -
Patent number: 8461659Abstract: According to one embodiment, in the upper laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. In the lower laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. The upper laminated structure and the lower laminated structure are equal in number of layers laminated therein. Each of the lowermost layer of the upper laminated structure and the uppermost layer of the lower laminated structure are configured by the first layer. The upper laminated structure and the lower laminated structure are configured to be asymmetric to each other such that, within some layer sets out of a plurality of layer sets each including two layers disposed at corresponding positions in the upper and lower laminated layers, one layer of the two layers in each layer set of the some layer sets is thinner than the other layer.Type: GrantFiled: March 21, 2011Date of Patent: June 11, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kokubun, Kazufumi Shiozawa
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Patent number: 8242532Abstract: According to one embodiment, a semiconductor light-emitting device having high light extraction efficiency is provided. The semiconductor light-emitting device includes a light transmissive substrate; a nitride semiconductor layer of a first conduction type formed on or above a top face side of the light transmissive substrate; an active layer made of nitride semiconductor formed on a top face of the nitride semiconductor layer of the first conduction type; a nitride semiconductor layer of a second conduction type formed on a top face of the active layer; a dielectric layer formed on a bottom face of the light transmissive substrate and having a refractive index lower than that of the light transmissive substrate; and a metal layer formed on a bottom face of the dielectric layer. And an interface between the light transmissive substrate and the dielectric layer is a uneven face, and an interface between the dielectric layer and the metal layer is a flat face.Type: GrantFiled: September 1, 2010Date of Patent: August 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue, Kazufumi Shiozawa, Takayoshi Fujii
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Patent number: 8188510Abstract: According to one embodiment, a semiconductor light-emitting device having high light extraction efficiency is provided. The semiconductor light-emitting device includes a light transmissive substrate; a nitride semiconductor layer of a first conduction type formed on or above a top face side of the light transmissive substrate; an active layer made of nitride semiconductor formed on a top face of the nitride semiconductor layer of the first conduction type; a nitride semiconductor layer of a second conduction type formed on a top face of the active layer; a dielectric layer formed on a bottom face of the light transmissive substrate and having a refractive index lower than that of the light transmissive substrate; and a metal layer formed on a bottom face of the dielectric layer. And an interface between the light transmissive substrate and the dielectric layer is a uneven face, and an interface between the dielectric layer and the metal layer is a flat face.Type: GrantFiled: September 1, 2010Date of Patent: May 29, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue, Kazufumi Shiozawa, Takayoshi Fujii
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SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
Publication number: 20120012874Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a translucent electrode. The substrate includes a first region provided along periphery of a first major surface and a second region provided on center side of the first major surface as viewed from the first region. The first semiconductor layer is provided on the first major surface of the substrate. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting layer. The translucent electrode is provided on the second semiconductor layer. A reflectance in the second region is higher than a reflectance in the first region.Type: ApplicationFiled: July 12, 2011Publication date: January 19, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Tomoko MORIOKA, Takayoshi Fujii, Toshitake Kitagawa, Kazufumi Shiozawa, Taisuke Sato, Hidefumi Yasuda, Yuko Kato -
Publication number: 20120001285Abstract: According to one embodiment, in the upper laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. In the lower laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. The upper laminated structure and the lower laminated structure are equal in number of layers laminated therein. Each of the lowermost layer of the upper laminated structure and the uppermost layer of the lower laminated structure are configured by the first layer. The upper laminated structure and the lower laminated structure are configured to be asymmetric to each other such that, within some layer sets out of a plurality of layer sets each including two layers disposed at corresponding positions in the upper and lower laminated layers, one layer of the two layers in each layer set of the some layer sets is thinner than the other layer.Type: ApplicationFiled: March 21, 2011Publication date: January 5, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Kokubun, Kazufumi Shiozawa
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Publication number: 20110308612Abstract: A thin film solar cell includes: a thin film-like substrate; an electrode arranged on the substrate; a photoelectric conversion layer stacked on the electrode; a transparent conductive film arranged on the photoelectric conversion layer; diffraction recessed portions provided periodically on a photoelectric conversion layer-side surface of the electrode; and reflection preventing recessed portions provided periodically on a photoelectric conversion layer-side surface of the transparent conductive film.Type: ApplicationFiled: June 17, 2011Publication date: December 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazufumi SHIOZAWA, Hiroyasu KONDO
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Publication number: 20110215370Abstract: According to one embodiment, a semiconductor light-emitting device having high light extraction efficiency is provided. The semiconductor light-emitting device includes a light transmissive substrate; a nitride semiconductor layer of a first conduction type formed on or above a top face side of the light transmissive substrate; an active layer made of nitride semiconductor formed on a top face of the nitride semiconductor layer of the first conduction type; a nitride semiconductor layer of a second conduction type formed on a top face of the active layer; a dielectric layer formed on a bottom face of the light transmissive substrate and having a refractive index lower than that of the light transmissive substrate; and a metal layer formed on a bottom face of the dielectric layer. And an interface between the light transmissive substrate and the dielectric layer is a uneven face, and an interface between the dielectric layer and the metal layer is a flat face.Type: ApplicationFiled: September 1, 2010Publication date: September 8, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue, Kazufumi Shiozawa, Takayoshi Fujii
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Publication number: 20100244168Abstract: A solid-state imaging device includes: a substrate including a plurality of light receiving sections; and a color filter including a guided-mode resonant grating provided immediately above each of the plurality of light receiving sections, at least one of an upper surface and a lower surface of the guided-mode resonant grating being covered with a layer having a lower refractive index than the guided-mode resonant grating.Type: ApplicationFiled: March 18, 2010Publication date: September 30, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Kazufumi SHIOZAWA, Yusaku Konno, Naotada Okada