Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A liquid crystal display drive and control device for reducing the number of exclusive signal interconnections for connecting a host module to a liquid crystal display driver for a sub-display, and peripheral devices, respectively. The liquid crystal display drive and control device includes, over one semiconductor substrate, a host interface circuit, a drive circuit, and an output port, and is used for connection with the host module. The drive circuit generates a drive signal for driving a liquid crystal display on the basis of information inputted to the host interface circuit before outputting. The output port is capable of controlling a logic level of an output signal on the basis of the information inputted to the host interface circuit. The liquid crystal display drive and control device is capable of distribute signals to circuits controlled by level signals with determined logic levels.

Abstract: It is intended to reduce the number of exclusive signal interconnections for connecting a host module to a liquid crystal display driver for a sub-display, and peripheral devices, respectively. A liquid crystal display drive and control device comprises, over one semiconductor substrate, a host interface circuit, a drive circuit, and an output port. The host interface circuit is used for connection with the host module. The drive circuit generates a drive signal for driving a liquid crystal display on the basis of information inputted to the host interface circuit before outputting. The output port is capable of controlling a logic level of an output signal on the basis of the information inputted to the host interface circuit.

Abstract: In an imaging apparatus, an imaging element picks up an object image focused thereon through an image pickup lens. An angle-rate sensor detects a shake amount of the imaging apparatus. An optical shake-compensation unit is prepared to move the image pickup lens based on the shake amount detected by the angle-rate sensor to compensate for a shake of the object image. A base plate shake-compensation unit is prepared to move the imaging element based on the shake amount detected by the angle-rate sensor to compensate for a shake of the object image and a control unit selectively controls operation of the optical shake-compensation unit and operation of the base plate shake-compensation unit, thereby compensating for a shake of the object image focused on the imaging element.

Abstract: A digital camera includes an imaging unit provided in a camera body to take an image electrically, an optical finder provided at an edge portion of the body, and a display apparatus provided in the body to display the taken image. The display apparatus includes a panel including a display area arranged nearer to a rear surface of the body than the imaging unit in the body, a projection projecting outwardly from a part of a periphery of the display area, a looking-out portion at a predetermined part of the projection, and a pixel drive unit for driving matrix pixels of the display area at the remaining part of the projection. In the body, the area of the panel corresponds to a window formed in the rear surface, the looking-out portion of the projection overlaps with the finder, and the drive unit is arranged in a side of the finder.

Abstract: An imaging apparatus can appropriately compensate for hand shake with less power consumption.

Abstract: It is intended to reduce the number of exclusive signal interconnections for connecting a host module to a liquid crystal display driver for a sub-display, and peripheral devices, respectively. A liquid crystal display drive and control device comprises, over one semiconductor substrate, a host interface circuit, a drive circuit, and an output port. The host interface circuit is used for connection with the host module. The drive circuit generates a drive signal for driving a liquid crystal display on the basis of information inputted to the host interface circuit before outputting. The output port is capable of controlling a logic level of an output signal on the basis of the information inputted to the host interface circuit.

Abstract: A digital camera includes an imaging unit provided in a camera body to take an image electrically, an optical finder provided at an edge portion of the body, and a display apparatus provided in the body to display the taken image. The display apparatus includes a panel including a display area arranged nearer to a rear surface of the body than the imaging unit in the body, a projection projecting outwardly from a part of a periphery of the display area, a looking-out portion at a predetermined part of the projection, and a pixel drive unit for driving matrix pixels of the display area at the remaining part of the projection. In the body, the area of the panel corresponds to a window formed in the rear surface, the looking-out portion of the projection overlaps with the finder, and the drive unit is arranged in a side of the finder.