Abstract: Provided is a pharmaceutical composition for treating a tumor, which is used in combination therapy of lenvatinib and (6S,9aS)—N-benzyl-8-({6-[3-(4-ethylpiperazin-1-yl)azetidin-1-yl]pyridin-2-yl}methyl)-6-(2-fluoro-4-hydroxybenzyl)-4,7-dioxo-2-(prop-2-en-1-yl)hexahydro-2H-pyrazino[2,1-c][1,2,4]triazine-1(6H)-carboxamide.

Abstract: Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.

Abstract: Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.

Abstract: A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.

Abstract: A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

Abstract: A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

Abstract: A through-hole layout apparatus includes: an extractor extracting an existing through-hole from design data for a semiconductor integrated circuit; a calculator calculating, for each through-hole extracted by the extractor, a layout density of through-holes in a predetermined region; a selector selecting a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor; and a through-hole adder determining, for each target through-hole selected by the selector, a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added.

Abstract: A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

Abstract: A semiconductor device which can prevent damage to an ESD protection device by pressure when bonding is carried out, while having a pad configuration that can ensure bonding reliability, with the semiconductor device being made as small as possible. A bonding area that is an area for wire bonding with respect to an external electrode pad and a probing area that is an area in which a probe needle is applied when probing, are provided, and the ESD protection device and a discharge path therefor are arranged below the probing area. Arranged below the bonding area are a support via that is a little smaller than the bonding pad, and a support pattern having a size corresponding to the bonding pad and joined to the bonding pad by the support via.

Abstract: An automatic wiring method of a semiconductor integrated circuit determines a wiring position based on layout data in which a plurality of cells corresponding to circuit elements of the semiconductor integrated circuit, which comprises the steps of when arranging a predetermined signal line extending in a first direction, extracting one or more coordinates in a second direction orthogonal to the first direction of all connecting terminals selected to be connected to the predetermined signal line among connecting terminals respectively included in the plurality of cells; calculating an average value of the extracted coordinates; and determining a position of the predetermined signal line in the second direction based on the average value.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: The present invention provides a semiconductor memory device comprising: memory cells; main decoders decoding address signals sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row address controlled by a single main word line in a basic cell in the word driver, and two of the main word line of the row address are made correspond to a half of lower-order 2-bits of the row address, and a word driver signal is placed inside of the basic cell of the word driver to prevent the word driver signal from being commonly used to adjacent two of the basic cell.

Abstract: The present invention provides a semiconductor memory device comprising: memory cells; main decoders decoding address signals; sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row address controlled by a single main word line in a basic cell in the word driver, and two of the main word line of the row address are made correspond to a half of lower-order 2-bits of the row address, and a word driver signal is placed inside of the basic cell of the word driver to prevent the word driver signal from being commonly used to adjacent two of the basic cell.

Abstract: A dynamic random access memory device selectively enters a flush write-in mode of operation, and has a plurality of controlling circuits respectively associated with a plurality of sense amplifier circuit groups which in turn are provided in association with a plurality of memory cell sub-arrays, wherein the plurality of controlling circuits produce activation signals respectively assigned the plurality of sense amplifier circuit groups in such a manner that time delay is introduced between activation of the sense amplifier circuits supplied with flush write data bits and activation of the sense amplifier circuits with refreshing data bits read out from non-selected memory cell groups, thereby preventing refresh data bits from undesirable data destruction without sacrifice of write-in speed.