Patents by Inventor Kazuhiko Nozawa

Kazuhiko Nozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090280376
    Abstract: A solid oxide fuel cell includes an electrolyte layer (101) made of a sintered product of a metal oxide powder, a fuel electrode (102) formed on one surface of the electrolyte layer (101), and an air electrode (103) formed on the other surface of the electrolyte layer (101) and including an active layer (131) and collector layer (132). The active layer (131) is made of a sintered product of a powder mixture obtained by mixing a powder of a perovskite oxide such as LaNi0.6Fe0.4O3 (LNF) having an average particle size of 0.5 ?m, and a powder of another perovskite oxide such as LNF having an average particle size of 1.3 ?m. The collector layer (132) is made of a sintered product of a powder of a perovskite oxide such as LNF having an average particle size of 1.3 ?m.
    Type: Application
    Filed: November 24, 2006
    Publication date: November 12, 2009
    Inventors: Reiichi Chiba, Yoshitaka Tabata, Takeshi Komatu, Himeko Ohrui, Kazuhiko Nozawa, Masayasu Arakawa
  • Patent number: 6940160
    Abstract: A semiconductor device comprising: a semiconductor element (10) having a plurality of electrodes (12); an interconnect pattern (20) electrically connected to the electrodes (12); a plurality of laminated insulating layers (41, 42 and 43); and a plurality of external terminals (30) electrically connected to the interconnect pattern (20). A plurality of holes (44, 46, and 48) are respectively formed in the insulating layers (41, 42, and 43) to form an opening portion (40) communicating from the hole (48) in the highest insulating layer (43) to the hole (44) in the lowest insulating layer (41). An external terminal (30) is provided within the opening portion (40), and the second hole (46) formed in the higher positioned second insulating layer (42) is larger than the first hole (44) formed in the lower positioned first insulating layer (41).
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: September 6, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Terunao Hanaoka, Haruki Ito, Kazuhiko Nozawa
  • Patent number: 6414390
    Abstract: A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal flyer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: July 2, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Kazuhiko Nozawa
  • Publication number: 20010000080
    Abstract: A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal layer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).
    Type: Application
    Filed: December 6, 2000
    Publication date: March 29, 2001
    Inventor: Kazuhiko Nozawa
  • Patent number: 6181010
    Abstract: A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal layer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: January 30, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Kazuhiko Nozawa