Patents by Inventor Kazuhiko Okawa
Kazuhiko Okawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10958263Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.Type: GrantFiled: March 10, 2020Date of Patent: March 23, 2021Assignee: SEIKO EPSON CORPORATIONInventors: Toshimichi Yamada, Tatsuro Shinmitsu, Kazuhiko Okawa, Hiroaki Nitta, Masahiro Hayashi
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Publication number: 20200295746Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.Type: ApplicationFiled: March 10, 2020Publication date: September 17, 2020Applicant: SEIKO EPSON CORPORATIONInventors: Toshimichi YAMADA, Tatsuro SHINMITSU, Kazuhiko OKAWA, Hiroaki NITTA, Masahiro HAYASHI
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Patent number: 8076748Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: GrantFiled: May 23, 2008Date of Patent: December 13, 2011Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Kazuhiko Okawa
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Publication number: 20080224219Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: ApplicationFiled: May 23, 2008Publication date: September 18, 2008Applicant: Seiko Epson CorporationInventors: Takayuki SAIKI, Kazuhiko Okawa
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Patent number: 7394134Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: GrantFiled: March 31, 2005Date of Patent: July 1, 2008Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Kazuhiko Okawa
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Patent number: 7242061Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.Type: GrantFiled: January 14, 2003Date of Patent: July 10, 2007Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
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Publication number: 20050218454Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: ApplicationFiled: March 31, 2005Publication date: October 6, 2005Inventors: Takayuki Saiki, Kazuhiko Okawa
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Patent number: 6894351Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.Type: GrantFiled: December 27, 2002Date of Patent: May 17, 2005Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
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Patent number: 6861705Abstract: Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors Tr1-Tr4 for connecting the gate electrodes of the transistors to the signal lines Ls, Ls1-Ls4 that are separated from the transistors Tr1-Tr4 by the dielectric layer 14. As a result, the time for an input signal to reach the entire area of the gate electrodes becomes shorter and a response to an input of a drive signal becomes faster.Type: GrantFiled: March 7, 2001Date of Patent: March 1, 2005Assignee: Seiko Epson CorporationInventors: Satoshi Ito, Kazuhiko Okawa
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Patent number: 6831334Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.Type: GrantFiled: May 30, 2001Date of Patent: December 14, 2004Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
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Patent number: 6671146Abstract: An electrostatic protection circuit of the present invention comprises: a first power supply terminal 1 to which a first voltage is applied; a second power supply terminal 2 to which a second voltage lower than the first voltage is applied; a first diode 12 connected in a reverse direction between the first and second power supply terminals; and a second diode 11 connected in a forward direction between the first and second power supply terminals. This configuration ensures that either one of the first and second diodes always operates in a forward direction to the static electricity applied between the first and second power supply terminals regardless of the polarity of the static electricity. Electrostatic charges therefore can be quickly absorbed through the diode in a forward direction.Type: GrantFiled: December 19, 2000Date of Patent: December 30, 2003Assignee: Seiko Epson CorporationInventors: Masami Hashimoto, Kazuhiko Okawa
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Patent number: 6653689Abstract: A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. An n-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.Type: GrantFiled: June 5, 2001Date of Patent: November 25, 2003Assignee: Seiko Epson CorporationInventor: Kazuhiko Okawa
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Patent number: 6631061Abstract: A semiconductor integrated device is provided which consists of a plurality of circuit blocks. Each circuit block is connected to a power supply terminal and a ground terminal. Signal interface sections connect signal circuits among the circuit blocks. A plurality of first diodes are serially connected to one another in a first direction between the ground terminal of a first one of the circuit blocks and the ground terminal of another of the circuit blocks. A plurality of second diodes are serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the first circuit block and the ground terminal of the another circuit block.Type: GrantFiled: December 26, 2000Date of Patent: October 7, 2003Assignee: Seiko Epson CorporationInventor: Kazuhiko Okawa
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Publication number: 20030151096Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.Type: ApplicationFiled: January 14, 2003Publication date: August 14, 2003Applicant: SEIKO EPSON CORPORATIONInventors: Kazuhiko Okawa, Takayuki Saiki
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Publication number: 20030141545Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.Type: ApplicationFiled: December 27, 2002Publication date: July 31, 2003Applicant: SEIKO EPSON CORPORATIONInventors: Kazuhiko Okawa, Takayuki Saiki
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Patent number: 6501155Abstract: To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source region 20 and the second edge 62 in an intermediate area is defined as L1, a distance between the first edge 60 and end edges 52-1 and 52-2 of a channel stopper non-implanted region 50 is defined as L1, a relation of L2? L1 is established. By providing the channel stopper non-implanted region 50, the ESD protection capability is improved. Also, by providing the cut sections 64-1 and 64-2 in a manner to satisfy the relation that is L2 is not less than L1, leak current is reduced. The source region 20 may also be provided with a cut section.Type: GrantFiled: November 23, 1998Date of Patent: December 31, 2002Assignee: Seiko Epson CorporationInventor: Kazuhiko Okawa
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Patent number: 6459139Abstract: The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.Type: GrantFiled: December 4, 2000Date of Patent: October 1, 2002Assignee: Seiko Epson CorporationInventors: Kunio Watanabe, Kazuhiko Okawa
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Patent number: 6455897Abstract: A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact.Type: GrantFiled: May 30, 2001Date of Patent: September 24, 2002Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
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Publication number: 20020030231Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.Type: ApplicationFiled: May 30, 2001Publication date: March 14, 2002Applicant: SEIKO EPSON CORPORATIONInventors: Kazuhiko Okawa, Takayuki Saiki
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Publication number: 20020030230Abstract: A semiconductor device including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact.Type: ApplicationFiled: May 30, 2001Publication date: March 14, 2002Applicant: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki