Patents by Inventor Kazuhiko Tomioka

Kazuhiko Tomioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6956783
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, input-output terminals, and a fuse block. A plurality of memory macros each having a plurality of memory cells is arranged on the semiconductor substrate. The insulating layer, which has a window portion, may be formed on the semiconductor substrate and covering the memory macros, the insulating layer having a window portion. The input-output terminals are arranged inline along an edge portion of the surface of the insulating layer. The input-output terminals transmit and receive signals between the memory macros and a circuit external to the semiconductor device. The fuse block is arranged in a space corresponding to the window portion in the insulating layer. The fuse block may include a plurality of fuse elements used to remedy defective portions of the plurality of memory cells in the plurality of memory macros.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: October 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Ikuta, Kazuhiko Tomioka
  • Publication number: 20030076715
    Abstract: A semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, input-output terminals, and a fuse block. A plurality of memory macros each having plurality of memory cells is arranged on the semiconductor substrate. The insulating layer, which has a window portion, may be formed on the semiconductor substrate and covering the memory macros, said insulating layer having a window portion. The input-output terminals are arranged inline along an edge portion of the surface of the insulating layer. The input-output terminals transmit and receive signals between the memory macros and a circuit external to the semiconductor device. The fuse block is arranged in a space corresponding to the window portion in the insulating layer. The fuse block may include a plurality of fuse elements used to remedy a defective memory cells in the memory macros.
    Type: Application
    Filed: June 12, 2002
    Publication date: April 24, 2003
    Inventors: Hiroaki Ikuta, Kazuhiko Tomioka
  • Patent number: 4931406
    Abstract: A method for manufacturing twin well type semi-conductor devices includes the steps of forming a first layer on a P-type silicon substrate, selectively removing part of the first layer to expose a predetermined portion of the surface of the substrate, ion-implanting phosphorus to introduce the phosphorus into the surface area of the substrate under the first layer and into a portion of the substrate deeper than the substrate surface area below the predetermined portion of the substrate surface, ion-implanting boron to introduce the boron into the surface area of the first layer and the surface area under the predetermined portion of the substrate, removing the first layer, and effecting heat treatment to diffuse the introduced phosphorus and boron.
    Type: Grant
    Filed: December 9, 1988
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiko Tomioka