Patents by Inventor Kazuhiko Yoshida
Kazuhiko Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7948725Abstract: A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.Type: GrantFiled: February 22, 2008Date of Patent: May 24, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventors: Shin Kiuchi, Kazuhiko Yoshida, Takeshi Ichimura, Naoki Yaezawa, Shoichi Furuhata
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Patent number: 7942750Abstract: A joint outer ring of a constant-velocity joint has a stem portion protruding from of a cup portion and inserted to a through hole of a hub in a bearing device. The joint outer ring has an abutment face abutting against an end face of a bearing inner ring fitted to an outer periphery of the hub in an outer bottom face of the cup portion, and is composed of a forged product of a steel material. The joint outer ring has a base material portion composed of a standard structure and an outer surface layer partially formed as a non-standard structure portion. The non-standard structure may be a tempered martensite structure, or a mixed structure including the tempered martensite structure and at least one of an upper bainite structure and a lower bainite structure.Type: GrantFiled: August 9, 2006Date of Patent: May 17, 2011Assignee: NTN CorporationInventors: Isao Hirai, Kazuhiko Yoshida
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Publication number: 20110107037Abstract: According to one embodiment, an information processing apparatus includes memory modules, a measuring module, a determination module, and a controller. The measuring module initializes the memory modules when the apparatus has been booted and an operating system of the information processing apparatus has not yet been started, measures a temperature of the memory modules at a time of the initialization, and measures a maximum temperature of each of the memory modules when the operating system is running. The determination module determines a first memory module, which has the least difference between the temperature at the time of the initialization and the maximum temperature at the time when the operating system is running, and a second memory module which has the lowest temperature at the time of the initialization. The controller maps memory addresses allocated to the first memory module in the second memory module, based on the temperatures.Type: ApplicationFiled: July 28, 2010Publication date: May 5, 2011Inventor: Kazuhiko Yoshida
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Patent number: 7910455Abstract: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.Type: GrantFiled: April 16, 2007Date of Patent: March 22, 2011Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
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Patent number: 7912417Abstract: An image forming apparatus includes: an image forming part; a first conveyance roller that conveys a recording medium to the image forming part; a forward/reverse-rotatable second conveyance roller, located between the first conveyance roller and the image forming part in a conveyance direction of the recording medium; a contact member, in contact with the second conveyance roller, that forms a nip between the second conveyance roller and the contact member; a first conveyance roller driver that rotate-drives the first conveyance roller in the same direction as the conveyance direction of the recording medium; and a drive transmission mechanism that performs drive transmission from the first conveyance roller driver to the second conveyance roller so as to start rotation of the second conveyance roller in a reverse direction of the conveyance direction of the recording medium before a lead edge of the recording medium arrives at the nip.Type: GrantFiled: December 12, 2006Date of Patent: March 22, 2011Assignee: Fuji Xerox Co., Ltd.Inventor: Kazuhiko Yoshida
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Publication number: 20110065519Abstract: Provided is a fixed type constant velocity universal joint of an eight-ball undercut-free type, which is capable of achieving an improvement of torque capacity at a high operating angle while ensuring durability at the time of a low operating angle. In the fixed type constant velocity universal joint of the eight-ball undercut-free type, a center of a track groove (32) of an outer joint member and a center of a track groove (35) of an inner joint member are separated from a joint center plane (P) respectively to both sides in an axial direction, and are offset to be positioned away from a joint center axis (X) to a radially opposite side relative to the track grooves (35). When Rt represents a distance between a center of a ball (37) and the center of the track groove (32) of the outer joint member, and F represents an axial distance between the joint center plane (P) and the center of the track groove (32) of the outer joint member, a ratio R1 between F and Rt is set to satisfy 0.061?R1?0.Type: ApplicationFiled: May 28, 2009Publication date: March 17, 2011Inventors: Keisuke Sone, Hirokazu Ooba, Kazuhiko Yoshida, Kiyohiro Itou
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Publication number: 20110003645Abstract: Provided is a constant velocity universal joint having high strength and capable of suppressing deformation caused by quenching at an opening end portion of a track groove of an outer joint member. In an undercut-free constant velocity universal joint in which a track groove (1d) in a cup portion (1a) of the outer joint member has a hardened layer (8a) formed by induction quenching, an opening end surface (1e) is protruded by a protruding amount t in an axial direction from a groove bottom (c) of the track groove (1d) in a relief surface (1f). The protruding amount t satisfies a relation of t=0.037 d to 0.185 d when a diameter of a torque transmission ball is represented by d. The opening end surface (1e) in a protruded portion (1i) and an outer surface (1j) of the cup portion (1a) continuous to the opening end surface (1e) have an unhardened layer free from hardening by quenching.Type: ApplicationFiled: September 22, 2008Publication date: January 6, 2011Inventors: Hirokazu Ooba, Kazuhiko Yoshida, Keisuke Sone
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Publication number: 20100323803Abstract: The present invention provides a constant velocity universal joint component and a manufacturing method thereof capable of achieving increased strength without significant procedural changes, and that can contribute to size reduction and weight reduction. In the constant velocity universal joint component of the present invention, a sharp-angled portion 15 is formed by machining after cold plastic working is applied. A carburization process is then performed in which surface carbon concentration of 0.45 mass % to less than 0.60 mass % is obtained. Quenching is then performed. High-frequency induction hardening is subsequently performed.Type: ApplicationFiled: January 28, 2008Publication date: December 23, 2010Inventor: Kazuhiko Yoshida
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Patent number: 7824106Abstract: A bearing device for a wheel enabling the easy control of quality since there is no possibility of cracking even if caulking is applied thereto. The bearing device comprises an outer ring having double rows of raceway surfaces on the inner periphery thereof, an inner member having raceway surfaces opposed to the raceway surfaces, and balls interposed between the double rows of raceway surfaces opposed to each other. The inner member further comprises a HUB ring and an inner ring. Caulking is applied to the HUB ring to join it to the inner ring. The grain size number of the austenite grains of a caulked section is at least 6.Type: GrantFiled: March 3, 2005Date of Patent: November 2, 2010Assignee: NTN CorporationInventors: Isao Hirai, Takayasu Takubo, Kazuhiko Yoshida
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Publication number: 20100264510Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.Type: ApplicationFiled: October 20, 2008Publication date: October 21, 2010Applicants: DENSO CORPORATION, Shin-Etsu Handotai Co., Ltd.Inventors: Hiroshi Ohtsuki, Mitsutaka Katada, Nobuhiko Noto, Hiroshi Takeno, Kazuhiko Yoshida
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Publication number: 20100234115Abstract: The present invention provides a compact constant velocity universal joint having high strength, and superior operability and durability. In the constant velocity universal joint of the present invention, an offset angle øT formed by a center of curvature OT0 of a guiding groove 2b of an outer component 2, an intersecting point Q between a joint plane P and a PCD, and a center of curvature OT1 of a guiding groove 3b of an inner component 3 is set to 11.0°?øT?15.0°.Type: ApplicationFiled: April 27, 2007Publication date: September 16, 2010Inventors: Kazuhiko Yoshida, Masazumi Kobayashi, Kazuhiro Azuma
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Publication number: 20100209285Abstract: A magnesium alloy for casting according to the present invention is characterized in that, when the entirety is taken as 100% by mass, it includes copper (Cu) in an amount of from 1% by mass or more to 5% by mass or less, calcium (Ca) in an amount of from 0.1% by mass or more to 5% by mass or less, tin (Sn) in an amount of from 0.1 or more to 3 or less by mass ratio with respect to the Ca (Sn/Ca); and the balance comprising magnesium (Mg) and inevitable impurities. By means of including Cu, Ca and Sn, crystallized substances of Mg—Ca—Sn compounds crystallize in crystalline grain boundaries between Mg crystalline grains as network shapes (three-dimensionally mesh shapes), along with Mg—Cu compounds. By means of the three-dimensionally mesh constructions, grain-boundary sliding, which becomes active especially when becoming high temperature, is suppressed, and thereby high-temperature strength and creep resistance at high temperature improve.Type: ApplicationFiled: April 14, 2008Publication date: August 19, 2010Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Yuki Okamoto, Kyoichi Kinoshita, Motoharu Tanizawa, Kazuhiko Yoshida
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Patent number: 7776453Abstract: A hub ring and/or an outer ring constituting a bearing device for a wheel, which is formed of a steel which contains 0.45 to 0.70 mass % of C and at least one of V, Nb and Ti in a total amount of 0.3 mass % or less, wherein a micro structure of a part being not surface-hardening-treated contains a ferrite in 15 to 30 area % and contains a particulate ferrite.Type: GrantFiled: March 3, 2005Date of Patent: August 17, 2010Assignee: NTN CorporationInventors: Isao Hirai, Takayasu Takubo, Kazuhiko Yoshida
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Publication number: 20100184923Abstract: An epoxy resin composition comprising, containing a solid epoxy resin (A) whose aromatic ring containing ratio is 5-40% obtained by reacting a polyester compound (b) possessing 1.2-1.8 of carboxylic group with a divalent epoxy resin (a) whose epoxy equivalent is 120-350 g/eq and a crosslinking agent (B) as essential components, and since a cured product obtained by curing said composition is superior in heat resistance, humid resistance and cracking resistance, said composition is useful in a field of electron material such as photo semi conductor sealing material, in particular useful for LED sealing.Type: ApplicationFiled: June 12, 2008Publication date: July 22, 2010Inventors: Kazuhiko Yoshida, Masao Gunji, Seigou Takuwa
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Patent number: 7727426Abstract: Disclosed is an epoxy resin composition which is solid at ordinary room temperature, cures with excellent light resistance and heat resistance and minimal shrinkage, and is useful for encapsulating LEDs. The epoxy resin composition is characterized by comprising as an essential component an epoxy resin having an epoxy equivalent of 300-1000 g/eq and a softening point of 65-110° C. obtained by reacting a nonaromatic polycarboxylic acid (A) having an acid value of 100-250 mgKOH/g with a nonaromatic epoxy resin (B) having an epoxy equivalent of 100-400 g/eq. The nonaromatic polycarboxylic acid (A) may be obtained by reacting 1,4-cyclohexanedimethanol, 2,2-bis(4-hydroxycyclohexyl)propane, or 3,9-bis(1,1-dimethyl-2-hydroxyethyl)-2,4,8,10-tetraoxaspiro[5,5]undecane with methylhexahydrophthalic acid or hexahydrophthalic acid.Type: GrantFiled: August 23, 2006Date of Patent: June 1, 2010Assignee: Nippon Steel Chemical Co., Ltd.Inventors: Kazumasa Kobayashi, Chiaki Asano, Hiroshi Sato, Yasuyuki Takeda, Kazuhiko Yoshida
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Publication number: 20100119405Abstract: A magnesium alloy for casting according to the present invention is characterized in that, when the entirety is taken as 100% by mass, it includes copper (Cu) in an amount of from 1% by mass or more to 5% by mass or less, calcium (Ca) in an amount of from 0.1% by mass or more to 5% by mass or less, silver (Ag) in an amount of from 0.1% by mass or more to 5% by mass or less, and the balance comprising magnesium (Mg) and inevitable impurities. By means of including Cu and Ca, crystallized substances of Mg—Ca compounds crystallize in crystalline grain boundaries between Mg crystalline grains as three-dimensionally mesh shapes, along with Mg—Cu compounds. By means of the three-dimensionally mesh constructions, grain-boundary sliding, which becomes active especially when becoming high temperature, is suppressed, and thereby high-temperature strength and creep resistance at high temperature improve.Type: ApplicationFiled: April 14, 2008Publication date: May 13, 2010Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Yuki Okamoto, Kyoichi Kinoshita, Motoharu Tanizawa, Kazuhiko Yoshida
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Publication number: 20100022038Abstract: The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer.Type: ApplicationFiled: October 18, 2007Publication date: January 28, 2010Applicant: SHIN-ETSU HANDOTAI CO., LTDInventors: Tsuyoshi Ohtsuki, Kazuhiko Yoshida
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Publication number: 20100019271Abstract: The present invention relates to an epoxy resin composition for optical semiconductor element encapsulation, the epoxy resin composition including following components (A) to (C): (A) an epoxy resin represented by the following structural formula (1): in which n is a positive number, (B) an epoxy resin except for the epoxy resin represented by the structural formula (1), and (C) a curing agent.Type: ApplicationFiled: July 27, 2009Publication date: January 28, 2010Applicant: NITTO DENKO CORPORATIONInventors: Shinya OTA, Kazuhiro FUKE, Chisato GOTO, Hisataka ITO, Takashi TANIGUCHI, Kazuhiko YOSHIDA, Masao GUNJI, Seigou TAKUWA
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Publication number: 20100016086Abstract: In the fixed type constant velocity universal joint, the center of each of the guide grooves of the outer joint member is offset to a position of being spaced apart from the joint central plane to the joint opening side by an axial distance (F), and being spaced apart from the joint central axis line to an opposite side in a radial direction with respect to each of the guide grooves by a radial distance (Fr). Further, the center of each of the guide grooves of the inner joint member is offset to a position of being spaced apart from the joint central plane to a joint innermost side by the axial distance (F), and being spaced apart from the joint central axis line to the opposite side in the radial direction with respect to each of the guide grooves by the radial distance (Fr).Type: ApplicationFiled: December 5, 2007Publication date: January 21, 2010Inventors: Keisuke Sone, Kazuhiko Yoshida, Hirokazu Ooba
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Publication number: 20090280620Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.Type: ApplicationFiled: April 23, 2007Publication date: November 12, 2009Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno