Patents by Inventor Kazuhiro Furuya

Kazuhiro Furuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9688889
    Abstract: [Problem] An object of the present invention is to provide a sealant composition for a nonaqueous electrolyte cell in which the application position and uniformity of applied film thickness of the sealant can be visually confirmed even when being applied as a thin film, and having excellent durability in relation to various electrolytic solutions used in the cell. [Solution] A sealant composition for a nonaqueous electrolyte cell, containing (A) an elastomer and (B) a cobalt blue colorant, in which the component (B) has a content of 0.1-20 mass parts with respect to 100 mass parts of the component (A).
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: June 27, 2017
    Assignee: THREE BOND FINE CHEMICAL CO., LTD.
    Inventors: Kazuhiro Furuya, Kanako Morii
  • Publication number: 20150240131
    Abstract: [Problem] An object of the present invention is to provide a sealant composition for a nonaqueous electrolyte cell in which the application position and uniformity of applied film thickness of the sealant can be visually confirmed even when being applied as a thin film, and having excellent durability in relation to various electrolytic solutions used in the cell. [Solution] A sealant composition for a nonaqueous electrolyte cell, containing (A) an elastomer and (B) a cobalt blue colorant, in which the component (B) has a content of 0.1-20 mass parts with respect to 100 mass parts of the component (A).
    Type: Application
    Filed: September 12, 2013
    Publication date: August 27, 2015
    Applicant: THREE BOND FINE CHEMICAL CO., LTD.
    Inventors: Kazuhiro Furuya, Kanako Morii
  • Patent number: 7948228
    Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 24, 2011
    Assignee: Fujitsu Limited
    Inventors: Takahito Takemoto, Akihiko Harada, Kazuhiro Furuya
  • Publication number: 20100052726
    Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
    Type: Application
    Filed: November 9, 2009
    Publication date: March 4, 2010
    Applicant: Fujitsu Limited
    Inventors: Takahito TAKEMOTO, Akihiko Harada, Kazuhiro Furuya
  • Patent number: 7635986
    Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: December 22, 2009
    Assignee: Fujitsu Limited
    Inventors: Takahito Takemoto, Akihiko Harada, Kazuhiro Furuya
  • Publication number: 20080106324
    Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
    Type: Application
    Filed: April 19, 2007
    Publication date: May 8, 2008
    Applicant: Fujitsu Limited
    Inventors: Takahito TAKEMOTO, Akihiko Harada, Kazuhiro Furuya
  • Patent number: 7135742
    Abstract: An insulated gate type semiconductor device comprised of a semiconductor layer serving as an active region isolated from a semiconductor substrate by a substrate isolation insulating film and a T-shaped gate electrode comprised of a trunk-shaped main gate electrode and a crosspiece-shaped conductor pattern provided on the semiconductor layer, wherein the thickness of the gate insulating film directly under the crosspiece-shaped conductor pattern is made greater than the thickness of the gate insulating film directly under the main gate electrode, whereby it is possible to prevent short-circuits between electrodes, prevent short-circuits between separators, and prevent an increase of the parasitic capacitance.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: November 14, 2006
    Assignee: Fujitsu Limited
    Inventors: Akihiko Harada, Sadanori Akiya, Kazuhiro Furuya, Hisashi Watanabe