Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.

Abstract: According to one embodiment, a storage system includes a network interface controller, a volatile memory and a storage device. The network interface controller is configured to communicate with a client using remote direct memory access. The network interface controller is configured to store write data and a submission queue entry including a write request of the write data transferred using the remote direct memory access in the volatile memory. The storage device is configured to write, when the submission queue entry is stored in a submission queue of the volatile memory, the write data to the storage device based on the submission queue entry.

Abstract: According to one embodiment, an information processing system includes a memory system including a non-volatile memory, and a host device including a host memory and a processor executing software for accessing data stored in the non-volatile memory. The processor is configured to: allocate a cache area in the host memory to cache data stored in the non-volatile memory; when the software is executed, perform a tag lookup of the cache area, and in a case where a cache hit has occurred upon the lookup, access the cache area without accessing the non-volatile memory; and refill the data stored in the non-volatile memory into the cache area at a second frequency lower than a first frequency at which a cache miss occurs.

Abstract: A storage system is provided, including: a host including a memory, the memory including a submission queue and a completion queue and being configured to store update frequency information; and a memory system configured to be connectable with the host and including a nonvolatile memory and a controller, the controller configured to control the nonvolatile memory, to receive the update frequency information of the submission queue from the host, to read command information stored in the submission queue based on the received update frequency information, and to execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a storage system includes a processor, a storage device, and a first memory. The storage device includes a nonvolatile memory, a control circuit, and a second memory. The processor retrieves, based on a retrieval key and retrieval information stored in the first memory, location information of data including the retrieval key and a value, and transmits the location information and the retrieval key to the control circuit. The control circuit reads the data from the nonvolatile memory based on the location information and the retrieval key, stores the data in the second memory, retrieves the value corresponding to the retrieval key from the data, and transmits the value to the processor.

Abstract: According to one embodiment, a storage system includes a processor, a storage device, and a first memory. The storage device includes a nonvolatile memory, a control circuit, and a second memory. The processor retrieves, based on a retrieval key and retrieval information stored in the first memory, location information of data including the retrieval key and a value, and transmits the location information and the retrieval key to the control circuit. The control circuit reads the data from the nonvolatile memory based on the location information and the retrieval key, stores the data in the second memory, retrieves the value corresponding to the retrieval key from the data, and transmits the value to the processor.

Abstract: According to one embodiment, a controller of a memory system manages 2N banks obtained by dividing a logical address space, and 2N regions included in a nonvolatile memory, the 2N regions corresponding one-to-one to the 2N banks. The controller stores an address translation table in a random access memory, the address translation table including a plurality of entries respectively corresponding to a plurality of logical addresses which are contiguous in units of a first size corresponding to granularity of data read/write-accessed by a host, the address translation table managing mapping between each of the logical addresses and each of physical addresses. The controller allocates 2N write buffers to the random access memory.

Abstract: A storage system includes: a storage device including a memory and a memory controller; a first device coupled to the storage device; and a control part. The control part is configured to: store, in a first storing device, a first order that orders the storage device to read first data from the memory; and store a second order in a second storing device. The second order orders the first device to transmit a first request to the storage device. The first request requests the first data to be transferred to the first device. The first device is configured to start processing the second order before completion of the reading of the first data from the memory.

Abstract: According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.

Abstract: A storage system is provided, including: a host including a memory, the memory including a submission queue and a completion queue and being configured to store update frequency information; and a memory system configured to be connectable with the host and including a nonvolatile memory and a controller, the controller configured to control the nonvolatile memory, to receive the update frequency information of the submission queue from the host, to read command information stored in the submission queue based on the received update frequency information, and to execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a data processing device includes: a first memory system including a first nonvolatile memory; a second memory system including a second nonvolatile memory; and a host device configured to control the first memory system and the second memory system. The first memory system further includes: a first circuit configured to cause the first nonvolatile memory to perform a read operation of first data based on a first request received from the host device; a second circuit capable of calculating a first access information corresponding to the second memory system based on the first data; and a third circuit configured to generate a second request to cause the second memory system to perform a read operation of second data based on the first access information.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to be connectable with a host and control the nonvolatile memory. The controller is configured to receive update frequency information of a submission queue from the host, read command information stored in the submission queue in accordance with the update frequency information, and execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.

Abstract: According to one embodiment, a storage system includes a network interface controller, a volatile memory and a storage device. The network interface controller is configured to communicate with a client using remote direct memory access. The network interface controller is configured to store write data and a submission queue entry including a write request of the write data transferred using the remote direct memory access in the volatile memory. The storage device is configured to write, when the submission queue entry is stored in a submission queue of the volatile memory, the write data to the storage device based on the submission queue entry.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to be connectable with a host and control the nonvolatile memory. The controller is configured to receive update frequency information of a submission queue from the host, read command information stored in the submission queue in accordance with the update frequency information, and execute controlling for the nonvolatile memory based on the command information.

Abstract: According to one embodiment, a storage system includes a processor, a storage device, and a first memory. The storage device includes a nonvolatile memory, a control circuit, and a second memory. The processor retrieves, based on a retrieval key and retrieval information stored in the first memory, location information of data including the retrieval key and a value, and transmits the location information and the retrieval key to the control circuit. The control circuit reads the data from the nonvolatile memory based on the location information and the retrieval key, stores the data in the second memory, retrieves the value corresponding to the retrieval key from the data, and transmits the value to the processor.

Abstract: According to one embodiment, a solid-state imaging device includes a pixel array, a scanning circuit, signal lines, processing circuits, and connection parts. One processing circuit and the signal lines are provided per one pixel column of the pixel array. The signal lines include a first signal line and a second signal line. Each pixel column includes first pixels and second pixels. The first pixels are configured to output pixel signals to the first signal line. The second pixels are configured to output pixel signals to the second signal line. When the scanning circuit simultaneously selects a first pixel row and a second pixel row, the connection parts connect the first signal line and the second signal line of each pixel column to different processing circuits. The first pixel row includes the first pixels. The second pixel row includes the second pixels.

Abstract: According to one embodiment, an image processing device includes a shift estimator, and a de-mosaic module. The shift estimator is configured to estimate a shift amount between a first pixel in a first image and a corresponding second pixel in a second image. The first image is taken by a first image pickup apparatus, and the second image is taken by a second image pickup apparatus. A focus position of the first image pickup apparatus is different from a focus position of the second image pickup apparatus. The de-mosaic module is configured to generate a first de-mosaic image by performing de-mosaic processing on each pixel in the first pixel using a pixel value of the corresponding second pixel, when the first pixel is determined to be in a state of in-focus based on the shift amount.

Abstract: According to one embodiment, a signal processing circuit includes a defect correction circuit. The defect correction circuit includes a color difference calculation part, a color difference sorting part, and a correction amount calculation part. The color difference calculation part is configured to calculate a difference between a signal level of a first pixel and a signal level of a second pixel in a pixel group. The pixel group includes pixels juxtaposed in a horizontal direction with a target pixel at a center. The correction amount calculation part is configured to calculate a correction amount for the target pixel, based on a difference chosen by the color difference sorting part and a signal level of a second pixel adjacent to the target pixel.

Abstract: According to one embodiment, an image processing device includes a line memory that stores an input image by a plurality of rows; a defect correcting circuit that performs defect correction on the input image based on image data stored in the line memory; a binning circuit that generates a low pass image having a lower spatial frequency than the input image by binning the input image subjected to the defect correction; a frame buffer that stores the low pass image; a filter that generates a high pass image having a higher spatial frequency than the low pass image by filtering the input image subjected to the defect correction; and a mixing circuit that mixes the low pass image with the high pass image.