Patents by Inventor Kazuhiro Ikemura
Kazuhiro Ikemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190044037Abstract: A ceramic plate having a flat plate shape includes a cut-out portion that is cut out inwardly from a peripheral end surface. An end surface defining the cut-put portion inclines in a thickness direction of the ceramic plate.Type: ApplicationFiled: September 2, 2016Publication date: February 7, 2019Applicant: NITTO DENKO CORPORATIONInventors: Hironaka FUJII, Yasuhiro AMANO, Kazuhiro IKEMURA
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Patent number: 8525351Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.Type: GrantFiled: August 10, 2011Date of Patent: September 3, 2013Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20110291303Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Applicants: Nitto Denko Corporation, Dai Nippon Printing Co., Ltd.Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Patent number: 8018044Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.Type: GrantFiled: July 13, 2005Date of Patent: September 13, 2011Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Patent number: 7943427Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.Type: GrantFiled: July 13, 2005Date of Patent: May 17, 2011Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20100193972Abstract: A resin composition for semiconductor encapsulation having good moldability, of which the cured product has effective electromagnetic wave shieldability, is provided. A resin composition for semiconductor encapsulation, containing spherical sintered ferrite particles having the following properties (a) to (c) : (a) the soluble ion content of the particles is at most 5 ppm; (b) the mean particle size of the particles is from 10 to 50 ?m; (c) the crystal structure of the particles by X-ray diffractiometry is a spinel structure.Type: ApplicationFiled: June 6, 2006Publication date: August 5, 2010Applicants: NITTO DENKO CORPORATION, TODA KOGYO CORP.Inventors: Kazumi Yamamoto, Masaharu Abe, Shigehisa Yamamoto, Kazushi Nishimoto, Tomohiro Dote, Kazumasa Igarashi, Kazuhiro Ikemura, Takuya Eto, Masataka Tada, Katsumi Okayama, Kaoru Kato
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Patent number: 7501711Abstract: An epoxy resin composition for semiconductor encapsulation which does not contain conductive foreign metallic particles having such a size that they cannot be detected and eliminated by the conventional method for eliminating conductive foreign metallic particles. The epoxy resin composition for semiconductor encapsulation comprises the following components (A) to (D). Conductive foreign metallic particles having a size of 20 ?m or more are substantially not contained in the aforementioned epoxy resin composition. (A) An epoxy resin. (B) A phenol resin. (C) A hardening accelerator. (D) An inorganic filler.Type: GrantFiled: October 18, 2005Date of Patent: March 10, 2009Assignee: Nitto Denko CorporationInventors: Takuya Eto, Kazuhiro Ikemura, Eiji Toyoda, Katsuyuki Nakabayashi, Daisuke Tsukahara
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Publication number: 20080136048Abstract: An epoxy resin composition for semiconductor encapsulation which does not contain conductive foreign metallic particles having such a size that they cannot be detected and eliminated by the conventional method for eliminating conductive foreign metallic particles. The epoxy resin composition for semiconductor encapsulation comprises the following components (A) to (D). Conductive foreign metallic particles having a size of 20 ?M or more are substantially not contained in the aforementioned epoxy resin composition. (A) An epoxy resin. (B) A phenol resin. (C) A hardening accelerator. (D) An inorganic filler.Type: ApplicationFiled: October 18, 2005Publication date: June 12, 2008Inventors: Takuya Eto, Kazuhiro Ikemura, Eiji Toyoda, Katsuyuki Nakabayashi, Daisuke Tsukahara
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Patent number: 7365441Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.Type: GrantFiled: February 28, 2006Date of Patent: April 29, 2008Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20080048311Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.Type: ApplicationFiled: July 13, 2005Publication date: February 28, 2008Applicants: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20070241445Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.Type: ApplicationFiled: July 13, 2005Publication date: October 18, 2007Applicants: DAI NIPPON PRINTING CO., LTD., NITTO DENKO CORPORATIONInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Patent number: 7268191Abstract: A method for producing an epoxy resin composition for semiconductor encapsulation, which does not cause void generation and the like and is excellent in reliability. A method for producing an epoxy resin composition for semiconductor encapsulation, which contains the following components (A) to (C): (A) an epoxy resin, (B) a phenol resin, and (C) a hardening accelerator, which comprises mixing the whole or a part of the components excluding the component (A) among the components containing the components (A) to (C) in advance under a reduced pressure of from 1.333 to 66.65 kPa and under a heating condition of from 100 to 230° C., and then mixing the component (A) and remaining components with the resulting mixture.Type: GrantFiled: December 2, 2004Date of Patent: September 11, 2007Assignee: Nitto Denko CorporationInventors: Eiji Toyoda, Takeshi Okada, Keisuke Yoshikawa, Takuya Eto, Kazuhiro Ikemura, Shinya Akizuki, Tsuyoshi Ishizaka, Takahiro Uchida, Kei Toyota
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Patent number: 7265167Abstract: An epoxy resin composition for semiconductor encapsulation capable of giving semiconductor devices of high reliability that do not cause short circuits even in pitch reduction in the interconnection electrode distance or the conductor wire distance therein as well as a semiconductor device using the same. The epoxy resin composition for semiconductor encapsulation, which comprises the following components (A) to (C): (A) an epoxy resin, (B) a phenolic resin, and (C) an inorganic filler for preventing semiconductors from short-circuiting in a step of semiconductor encapsulation.Type: GrantFiled: November 10, 2003Date of Patent: September 4, 2007Assignee: Nitto Denko CorporationInventors: Shinya Akizuki, Kazuhiro Ikemura, Hisataka Ito, Takahiro Uchida, Takuya Eto, Tsutomu Nishioka, Katsumi Shimada
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Patent number: 7262514Abstract: An epoxy resin composition for semiconductor encapsulation in producing surface mount lead-less thin semiconductor devices. The epoxy resin composition for surface mount lead-less semiconductor device encapsulation which device comprising an encapsulating resin layer and, encapsulated therein, a substrate, a semiconductor element mounted on the substrate, two or more conductive parts disposed around the semiconductor element, and wires which electrically connect electrodes of the semiconductor element to the conductive parts, wherein the bottom face of the substrate and the bottom face of each conductive part are exposed without being encapsulated in the encapsulating resin layer, and the epoxy resin composition used for forming the encapsulating resin layer has the following properties (?) and (?): (?) a melt viscosity of 2-10 Pa.s at 175° C.; and (?) a flexural strength of cured state of 130 MPa or higher at ordinary temperature.Type: GrantFiled: April 27, 2005Date of Patent: August 28, 2007Assignee: Nitto Denko CorporationInventors: Keisuke Yoshikawa, Kazuhito Hosokawa, Takuji Okeyui, Kazuhiro Ikemura
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Patent number: 7132755Abstract: An adhesive film for manufacturing a semiconductor device comprising a thermosetting adhesive layer and a heat-resistant backing layer, wherein the adhesive film is applied to a method for manufacturing a semiconductor device, comprising the steps of (a) embedding at least a part of a conductor in the adhesive film to form a conductor adhered thereto; (b) mounting a semiconductor chip on the conductor; (c) connecting the semiconductor chip to the conductor; (d) encapsulating the semiconductor chip with an encapsulation resin; and (e) removing the adhesive film therefrom. The adhesive film can be suitably used for manufacturing a semiconductor device having a so-called standoff wherein a part of a conductor is projecting from an encapsulation resin.Type: GrantFiled: December 16, 2004Date of Patent: November 7, 2006Assignee: Nitto Denko CorporationInventors: Kazuhito Hosokawa, Takuji Okeyui, Kazuhiro Ikemura, Keisuke Yoshikawa
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Publication number: 20060145363Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.Type: ApplicationFiled: February 28, 2006Publication date: July 6, 2006Applicants: DAI NIPPON PRINTING CO., LTD., NITTO DENKO CORPORATIONInventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Patent number: 7064011Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.Type: GrantFiled: February 20, 2004Date of Patent: June 20, 2006Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20050253286Abstract: An epoxy resin composition for semiconductor encapsulation in producing surface mount lead-less thin semiconductor devices. The epoxy resin composition for surface mount lead-less semiconductor device encapsulation which device comprising an encapsulating resin layer and, encapsulated therein, a substrate, a semiconductor element mounted on the substrate, two or more conductive parts disposed around the semiconductor element, and wires which electrically connect electrodes of the semiconductor element to the conductive parts, wherein the bottom face of the substrate and the bottom face of each conductive part are exposed without being encapsulated in the encapsulating resin layer, and the epoxy resin composition used for forming the encapsulating resin layer has the following properties (?) and (?): (?) a melt viscosity of 2-10 Pa.s at 175° C.; and (?) a flexural strength of cured state of 130 MPa or higher at ordinary temperature.Type: ApplicationFiled: April 27, 2005Publication date: November 17, 2005Inventors: Keisuke Yoshikawa, Kazuhito Hosokawa, Takuji Okeyui, Kazuhiro Ikemura
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Publication number: 20050154152Abstract: A method for producing an epoxy resin composition for semiconductor encapsulation, which does not cause void generation and the like and is excellent in reliability. A method for producing an epoxy resin composition for semiconductor encapsulation, which contains the following components (A) to (C): (A) an epoxy resin, (B) a phenol resin, and (C) a hardening accelerator, which comprises mixing the whole or a part of the components excluding the component (A) among the components containing the components (A) to (C) in advance under a reduced pressure of from 1.333 to 66.65 kPa and under a heating condition of from 100 to 230° C., and then mixing the component (A) and remaining components with the resulting mixture.Type: ApplicationFiled: December 2, 2004Publication date: July 14, 2005Inventors: Eiji Toyoda, Takeshi Okada, Keisuke Yoshikawa, Takuya Eto, Kazuhiro Ikemura, Shinya Akizuki, Tsuyoshi Ishizaka, Takahiro Uchida, Kei Toyota
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Publication number: 20050133936Abstract: An adhesive film for manufacturing a semiconductor device comprising a thermosetting adhesive layer and a heat-resistant backing layer, wherein the adhesive film is applied to a method for manufacturing a semiconductor device, comprising the steps of (a) embedding at least a part of a conductor in the adhesive film to form a conductor adhered thereto; (b) mounting a semiconductor chip on the conductor; (c) connecting the semiconductor chip to the conductor; (d) encapsulating the semiconductor chip with an encapsulation resin; and (e) removing the adhesive film therefrom. The adhesive film can be suitably used for manufacturing a semiconductor device having a so-called standoff wherein a part of a conductor is projecting from an encapsulation resin.Type: ApplicationFiled: December 16, 2004Publication date: June 23, 2005Inventors: Kazuhito Hosokawa, Takuji Okeyui, Kazuhiro Ikemura, Keisuke Yoshikawa