Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper.

Abstract: A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.

Abstract: A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper.

Abstract: A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

Abstract: A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A nitride semiconductor device includes: first electrode interconnect layers extending in parallel with one another over the nitride semiconductor layer and divided by areas extending across a longitudinal direction of the first electrode interconnect layers; first gate electrodes extending along the first electrode interconnect layers; first gate electrode connecting interconnects extending in associated ones of the areas dividing the first electrode interconnect layers and being in connection to the first gate electrodes; first electrode connecting interconnects formed above the first gate electrode connecting interconnects and being in connection to the first electrode interconnect layers; a first electrode upper interconnects formed on the first electrode connecting interconnects with an interconnect insulating film interposed therebetween, and being in connection to the first electrode connecting interconnects through associated ones of openings of the interconnect insulating film.

Abstract: A nitride semiconductor device includes a nitride semiconductor multilayer including an active region, and first and second electrodes, each having a finger-like structure and formed on the active region to be spaced from each other. A first electrode interconnect is formed on the first electrode. A second electrode interconnect is formed on the second electrode. A second insulating film is formed to cover the first and second electrode interconnects. A first metal layer is formed on the second insulating film. The first metal layer is formed above the active region with the second insulating film interposed therebetween, and is coupled to the first electrode interconnect.

Abstract: A nitride semiconductor device includes: first electrode interconnect layers extending in parallel with one another over the nitride semiconductor layer and divided by areas extending across a longitudinal direction of the first electrode interconnect layers; first gate electrodes extending along the first electrode interconnect layers; first gate electrode connecting interconnects extending in associated ones of the areas dividing the first electrode interconnect layers and being in connection to the first gate electrodes; first electrode connecting interconnects formed above the first gate electrode connecting interconnects and being in connection to the first electrode interconnect layers; a first electrode upper interconnects formed on the first electrode connecting interconnects with an interconnect insulating film interposed therebetween, and being in connection to the first electrode connecting interconnects through associated ones of openings of the interconnect insulating film.

Abstract: A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film formed between the source electrode and the drain electrode.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film formed between the source electrode and the drain electrode.