Patents by Inventor Kazuhiro Kijima

Kazuhiro Kijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10505569
    Abstract: An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Naito, Noriyoshi Izumi, Kazuhiro Kijima
  • Publication number: 20190181888
    Abstract: An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.
    Type: Application
    Filed: October 8, 2018
    Publication date: June 13, 2019
    Inventors: Wataru NAITO, Noriyoshi IZUMI, Kazuhiro KIJIMA
  • Patent number: 10064131
    Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Kijima, Wataru Naito
  • Publication number: 20180049119
    Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Inventors: Kazuhiro KIJIMA, Wataru NAITO
  • Patent number: 9832724
    Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELCTRONICS CORPORATION
    Inventors: Kazuhiro Kijima, Wataru Naito
  • Publication number: 20170094596
    Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.
    Type: Application
    Filed: August 9, 2016
    Publication date: March 30, 2017
    Inventors: Kazuhiro KIJIMA, Wataru NAITO
  • Publication number: 20170085270
    Abstract: An object is to avoid a deadlock in a PLL. A PLL synthesizer includes a PLL circuit that includes a voltage control oscillation circuit configured to control an oscillation frequency according to a control voltage, an oscillation frequency storage unit configured to previously store the oscillation frequency at a first temperature, a control voltage setting unit configured to set a control voltage based on a difference between the oscillation frequency at a second temperature and the stored oscillation frequency, and a calibration processing unit configured to calibrate the voltage control oscillation circuit in a state in which the control voltage is set so that the oscillation frequency will become a predetermined frequency.
    Type: Application
    Filed: July 29, 2016
    Publication date: March 23, 2017
    Inventors: Hidehiko SUZUKI, Naoki KOIZUMI, Hisaya ISHIHARA, Kazuhiro KIJIMA
  • Patent number: 7936071
    Abstract: A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: May 3, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Masaaki Abe, Kazuhiro Kijima
  • Patent number: 7744965
    Abstract: The present invention provides a method and apparatus for forming a zinc oxide thin film with high transparency and high conductivity on a surface of a flexible substrate such as plastic without the indispensable requirement of doping impurities. In the method of forming a zinc oxide thin film by reacting oxygen radicals and zinc atoms on a surface of a substrate placed in a film-forming chamber evacuated to a vacuum, the density of crystal defects that are defects of the atomic arrangement of the zinc oxide thin film is controlled by the temperature of the substrate, and the zinc oxide thin film is thereby formed. It is suitable to form the film while maintaining the temperature of the substrate at 400° C. or less to intentionally disturb the regularity of the atomic arrangement of the zinc oxide thin film.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: June 29, 2010
    Assignees: Yamanashi University, Yamanashi Prefecture, Nakaya Ltd.
    Inventors: Takashi Matsumoto, Chitake Imazu, Shigeru Hagihara, Kazuhiro Kijima, Osamu Abe, Satoshi Hiraki, Yuichiro Fujikawa
  • Patent number: 7598730
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 6, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hideki Yuzawa, Kazuhiro Kijima
  • Patent number: 7573256
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 11, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hideki Yuzawa, Kazuhiro Kijima
  • Publication number: 20080088024
    Abstract: A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.
    Type: Application
    Filed: November 27, 2007
    Publication date: April 17, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masaaki ABE, Kazuhiro KIJIMA
  • Publication number: 20070259458
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 10, 2007
    Publication date: November 8, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA
  • Publication number: 20070259461
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 10, 2007
    Publication date: November 8, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA
  • Publication number: 20070259460
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 10, 2007
    Publication date: November 8, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA
  • Publication number: 20070259459
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 10, 2007
    Publication date: November 8, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA
  • Publication number: 20070254388
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 10, 2007
    Publication date: November 1, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA
  • Publication number: 20070042216
    Abstract: The present invention provides a method and apparatus for forming a zinc oxide thin film with high transparency and high conductivity on a surface of a flexible substrate such as plastic without the indispensable requirement of doping impurities. In the method of forming a zinc oxide thin film by reacting oxygen radicals and zinc atoms on a surface of a substrate placed in a film-forming chamber evacuated to a vacuum, the density of crystal defects that are defects of the atomic arrangement of the zinc oxide thin film is controlled by the temperature of the substrate, and the zinc oxide thin film is thereby formed. It is suitable to form the film while maintaining the temperature of the substrate at 400° C. or less to intentionally disturb the regularity of the atomic arrangement of the zinc oxide thin film.
    Type: Application
    Filed: March 17, 2006
    Publication date: February 22, 2007
    Applicants: Yamanashi University, YAMANASHI PREFECTURE, NAKAYA ltd.
    Inventors: Takashi Matsumoto, Chitake Imazu, Shigeru Hagihara, Kazuhiro Kijima, Osamu Abe, Satoshi Hiraki, Yuichiro Fujikawa
  • Publication number: 20070026661
    Abstract: A method of manufacturing a semiconductor device includes: (a) preparing a semiconductor chip having a plurality of electrodes; (b) preparing a substrate having a plurality of electrical connection portions; (c) holding the semiconductor chip by a holding tool; (d) planarizing an upper surface of the electrode of the semiconductor chip held by the holding tool; and (e) electrically connecting, after the step (d), the electrode of the semiconductor chip and the electrical connection portion of the substrate.
    Type: Application
    Filed: July 20, 2006
    Publication date: February 1, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Michiyoshi TAKANO, Kazuhiro KIJIMA
  • Publication number: 20070018675
    Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 25, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideki YUZAWA, Kazuhiro KIJIMA