Patents by Inventor Kazuhiro Komori
Kazuhiro Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5300802Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.Type: GrantFiled: May 20, 1991Date of Patent: April 5, 1994Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
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Patent number: 5235200Abstract: Herein disclosed is a semiconductor integrated circuit device having a nonvolatile memory function and including a memory cell composed of a field effect transistor having a floating gate electrode and a control gate electrode. A first insulating film for element isolation is buried between the floating gate electrodes. The size of the drain region of the field effect transistor is substantially regulated by both the gap between the first insulating films adjacent to the drain region and the gap between the control gate electrodes adjacent to the drain region. The gaps between the data line at the connection portion with the drain region and the first insulating films individually adjacent to the drain region are equalized. The gaps between the data line at the connection portion with the drain region and the floating gate electrodes or control gate electrodes individually adjacent to the drain region are equalized.Type: GrantFiled: November 1, 1990Date of Patent: August 10, 1993Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Toshiaki Nishimoto
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Patent number: 5194924Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: October 23, 1991Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
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Patent number: 5189497Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.Type: GrantFiled: September 24, 1991Date of Patent: February 23, 1993Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 5155701Abstract: An EPROM and a method of testing the former, in which a defective memory cell caused by defects in the insulating films between a substrate and a floating gate and between the floating gate and a control gate can be tested without writing any data in the individual memory cells by holding data lines to a low potential and word lines fed with a voltage.Type: GrantFiled: June 8, 1990Date of Patent: October 13, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Yuji Hara, Hideaki Takahashi, Minoru Fukuda, Satoshi Meguro
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Patent number: 5153144Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.Type: GrantFiled: November 18, 1991Date of Patent: October 6, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Yamamoto
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Patent number: 5098855Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of a LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: March 28, 1990Date of Patent: March 24, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
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Patent number: 5079603Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.Type: GrantFiled: April 30, 1990Date of Patent: January 7, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
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Patent number: 4996571Abstract: The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.Type: GrantFiled: July 6, 1989Date of Patent: February 26, 1991Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hitoshi Kume, Yoshiaki Kamigaki, Tetsuo Adachi, Toshihisa Tsukada, Kazuhiro Komori, Toshiaki Nishimoto, Tadashi Muto, Toshiko Koizumi
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Patent number: 4972371Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.Type: GrantFiled: June 7, 1988Date of Patent: November 20, 1990Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Takaaki Hagiwara, Satoshi Meguro, Toshiaki Nishimoto, Takeshi Wada, Kiyofumi Uchibori, Tadashi Muto, Hitoshi Kume, Hideaki Yamamoto, Tetsuo Adachi, Toshihisa Tsukada, Toshiko Koizumi
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Patent number: 4918501Abstract: Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.Type: GrantFiled: December 29, 1988Date of Patent: April 17, 1990Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
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Patent number: 4904615Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Type: GrantFiled: January 26, 1989Date of Patent: February 27, 1990Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Kousuke Okuyama, Ken Uchida, Kouichi Kusuyama, Satoshi Meguro, Hisao Katto, Kazuhiro Komori
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Patent number: 4872041Abstract: Disclosed is a semiconductor device, and method of manufacture thereof, the device having a conductive layer formed on a semiconductor substrate, with an insulating layer interposed between the substrate and conductive layer, and wherein a dense insulating layer is disposed at the sides of the conductive layer so as to cover the sides of the insulating layer on the substrate, the dense insulating layer acting to increase retention of charge in the conductive layer. The conductive layer can be the floating gate of a field effect transistor, with a control gate formed on the floating gate via another insulating layer whose sides can also be covered by the dense insulating layer. Such field effect transistor, having the floating gate, can be used as the memory cell of an EPROM, with the charge being the data stored in the cell. A field effect transistor of a peripheral circuit of the EPROM can also have the dense insulating layer applied so as to cover the sides of the gate oxide layer thereof.Type: GrantFiled: February 24, 1988Date of Patent: October 3, 1989Assignee: Hitachi, Ltd.Inventors: June Sugiura, Kazuhiro Komori
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Patent number: 4818718Abstract: A semiconductor integrated circuit device, especially an EPROM (Electrically Programmable Read Only Memory) device which consists of an MIS type memory transistor portion having a floating gate electrode and a control gate electrode on said floating gate electrode, and of an MIS type transistor portion having a gate electrode is formed by patterning the same conductor layer as the floating gate electrode in the periphery of said MIS type memory transistor portion.Type: GrantFiled: October 3, 1986Date of Patent: April 4, 1989Assignee: Hitachi, LimitedInventors: Yasunobu Kosa, Kazuhiro Komori
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Patent number: 4818716Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Type: GrantFiled: October 22, 1987Date of Patent: April 4, 1989Assignees: Hitachi Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Kousuke Okuyama, Ken Uchida, Kouichi Kusuyama, Satoshi Meguro, Hisao Katto, Kazuhiro Komori
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Patent number: 4784968Abstract: Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.Type: GrantFiled: July 20, 1987Date of Patent: November 15, 1988Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, Kousuke Okuyama
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Patent number: 4764479Abstract: A semiconductor integrated circuit device, especially an EPROM (Electrically Programmable Read Only Memory) device which consists of an MIS type memory transistor portion having a floating gate electrode and a control gate electrode on said floating gate electrode, and of an MIS type transistor portion having a gate electrode is formed by patterning the same conductor layer as the floating gate electrode in the periphery of said MIS type memory transistor portion.Type: GrantFiled: August 15, 1986Date of Patent: August 16, 1988Assignee: Hitachi, LimitedInventors: Yasunobu Kosa, Kazuhiro Komori
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Patent number: 4697198Abstract: Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.Type: GrantFiled: August 8, 1985Date of Patent: September 29, 1987Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, Kousuke Okuyama
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Patent number: 4663645Abstract: A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.Type: GrantFiled: May 22, 1985Date of Patent: May 5, 1987Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Kenichi Kuroda, June Sugiura
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Patent number: 4653026Abstract: A nonvolatile memory device comprising a plurality of memory cells composed of insulated gate-type field effect semiconductor elements, terminals for applying a writing voltage and a reading voltage to said plurality of memory cells, wirings for connecting in common insulated gate-type field effect transistor elements of said plurality of memory cells, and resistance elements or MISFET's which are connected between the wirings and the terminals, wherein said resistance elements or MISFET's are composed of a polycrystalline silicon film or a single crystal silicon film formed on the field insulation film.Type: GrantFiled: July 29, 1982Date of Patent: March 24, 1987Assignee: Hitachi, Ltd.Inventors: Kazuhiro Komori, Satoshi Meguro, Satoru Ito, Toshimasa Kihara, Harumi Wakimoto