Abstract: A measurement result receiving apparatus receives measurement results transmitted from a plurality of measuring devices, the measurement results obtained by conducting a measurement at a predetermined sampling interval according to a reference clock of each measuring device. The measurement result receiving apparatus includes a receiving section that receives the measurement results from the plurality of measuring devices; and a sampling interval converting section that converts the measurement results into measurement values associated with a common sampling interval.

Abstract: A measurement result receiving apparatus receives measurement results transmitted from a plurality of measuring devices, the measurement results obtained by conducting a measurement at a predetermined sampling interval according to a reference clock of each measuring device. The measurement result receiving apparatus includes a receiving section that receives the measurement results from the plurality of measuring devices; and a sampling interval converting section that converts the measurement results into measurement values associated with a common sampling interval.

Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Abstract: Integrated circuit memory devices are tested by loading into a first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Automatic switching then takes place to a second defect interpretation memory. The results of a succeeding comparison test are loaded therein, while simultaneously analyzing results from the preceding comparison test in the first defect interpretation memory. Then, automatic switching back to the first defect interpretation memory takes place, and results of a next succeeding comparison test are loaded therein while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory. Automatic switching and automatic switching back are repeatedly performed, to thereby simultaneously test a memory device and analyze memory test results.

Abstract: A semiconductor memory testing apparatus of the present invention includes a signal generating unit for generating an input signal, an address signal and an expected value signal, a judging unit for judging a quality by comparing the output signal outputted by a semiconductor memory device under test with the expected value signal and generating a judgement signal, and a defect analyzing memory unit having a defect analyzing memory for storing the judgement signal. An address space of the address signal generated by the signal generating unit is set according to classification of the memory cells of the semiconductor memory device under test, and the signal generating unit includes an address space switching unit for switching over the address space as the necessity may arise. The defect analyzing memory unit sets a predetermined address in accordance with the address space to which the address signal belongs.