Patents by Inventor Kazuhisa Mori

Kazuhisa Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162222
    Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Hiroshi YANAGIGAWA, Hideki NIWAYAMA, Hiroyoshi KUDOU, Kazuhisa MORI, Kodai WADA
  • Publication number: 20240162143
    Abstract: In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Hiroshi YANAGIGAWA, Hideki NIWAYAMA, Hiroyoshi KUDOU, Kazuhisa MORI, Kodai WADA
  • Patent number: 11967294
    Abstract: A common electrode driver includes an inverting amplifier including a first resistor, a second resistor, and an operational amplifier, and a resistance ratio adjustment circuit that adjusts, in accordance with a length of one horizontal scan period, a resistance ratio being a ratio of a resistance value of the second resistor to a resistance value of the first resistor. A feedback voltage is provided to one end of the first resistor. The resistance ratio adjustment circuit sets the resistance ratio when second driving is performed, in which a length of one horizontal scan period is a second time longer than a first time, to be smaller than the resistance ratio when first driving is performed, in which a length of one horizontal scan period is the first time.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 23, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Masaki Uehata, Yasuki Mori, Kohji Saitoh, Takayuki Mizunaga, Kazuya Kondoh, Takashi Nojima, Kazuhisa Yoshimoto, Kosuke Kawamoto, Hiroyuki Kito, Kazuki Nakamichi
  • Publication number: 20230291401
    Abstract: Performance of a semiconductor device is enhanced. A loss of a circuit device using a semiconductor device as a switch is reduced. A semiconductor device includes: a first semiconductor chip having a first MOSFET of p-type and a first parasitic diode; and a second semiconductor chip having a second MOSFET of n-type and a second parasitic diode. On front surfaces of the first and second semiconductor chips, a first source electrode and a first gate wiring and a second source electrode and a second gate wiring are formed, respectively. On back surfaces of the first and second semiconductor chips, first and second drain electrodes are formed, respectively. The second back surface and the first front surface face each other such that the second drain electrode and the first source electrode come into contact with each other via a conductive paste.
    Type: Application
    Filed: November 29, 2022
    Publication date: September 14, 2023
    Inventors: Kazuhisa MORI, Toshiyuki HATA
  • Publication number: 20230246002
    Abstract: A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.
    Type: Application
    Filed: November 29, 2022
    Publication date: August 3, 2023
    Inventors: Yasutaka NAKASHIBA, Hiroshi YANAGIGAWA, Kazuhisa MORI, Toshiyuki HATA
  • Patent number: 11557648
    Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: January 17, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Yanagigawa, Katsumi Eikyu, Masami Sawada, Akihiro Shimomura, Kazuhisa Mori
  • Publication number: 20210217844
    Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.
    Type: Application
    Filed: December 8, 2020
    Publication date: July 15, 2021
    Inventors: Hiroshi YANAGIGAWA, Katsumi EIKYU, Masami SAWADA, Akihiro SHIMOMURA, Kazuhisa MORI
  • Patent number: 11004749
    Abstract: A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Q 1 and the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Q 2 is formed in the second element region RCM. The first power MOS transistor Q 1 includes a first trench gate electrode TGE1, and the second power MOS transistor Q 2 includes a second trench gate electrode TGE2. The depth GDP1 of the first trench gate electrode TGE1 is shallower than the depth GDP2 of the second trench gate electrode TGE2.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Moriya, Hiroshi Yanagigawa, Kazuhisa Mori
  • Publication number: 20200411683
    Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 31, 2020
    Inventors: Yoshinori KAYA, Katsumi EIKYU, Akihiro SHIMOMURA, Hiroshi YANAGIGAWA, Kazuhisa MORI
  • Publication number: 20200126977
    Abstract: A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Q 1 and the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Q 2 is formed in the second element region RCM. The first power MOS transistor Q 1 includes a first trench gate electrode TGE1, and the second power MOS transistor Q 2 includes a second trench gate electrode TGE2. The depth GDP1 of the first trench gate electrode TGE1 is shallower than the depth GDP2 of the second trench gate electrode TGE2.
    Type: Application
    Filed: September 17, 2019
    Publication date: April 23, 2020
    Inventors: Taro MORIYA, Hiroshi YANAGIGAWA, Kazuhisa MORI
  • Patent number: 10332993
    Abstract: A semiconductor device with a simplified structure including an energization control element and reverse coupling protection element, and a manufacturing method therefor. Its semiconductor substrate has deep and shallow trenches in its first surface. A first n-type impurity region lies in its second surface in contact with the deep trench bottom. A p-type impurity region includes: a p-type base region to make a pn junction with the first n-type region and in contact with the shallow trench bottom; and a back gate region joined to the p-type base region, lying in the first surface. A second n-type impurity region makes a pn junction with the p-type impurity region, lying in the first surface in contact with the shallow trench side face. An n+ source region makes a pn junction with the p-type region, lying in the first surface in contact with the side faces of deep and shallow trenches.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhisa Mori
  • Patent number: 10192795
    Abstract: A semiconductor device including a power transistor is prevented from being broken. A cathode of a temperature sensing diode and a source of a power MOSFET are electrically coupled to each other so as to have the same potential. Such a characteristic point allows the temperature sensing diode to be disposed in a power MOSFET formation region without considering withstand voltage. This means that there is no need to provide an isolating structure that maintains a withstand voltage between the power MOSFET and the temperature sensing diode. Consequently, the power MOSFET and the temperature sensing diode can be closely disposed.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhisa Mori
  • Publication number: 20180331210
    Abstract: A semiconductor device with a simplified structure including an energization control element and reverse coupling protection element, and a manufacturing method therefor. Its semiconductor substrate has deep and shallow trenches in its first surface. A first n-type impurity region lies in its second surface in contact with the deep trench bottom. A p-type impurity region includes: a p-type base region to make a pn junction with the first n-type region and in contact with the shallow trench bottom; and a back gate region joined to the p-type base region, lying in the first surface. A second n-type impurity region makes a pn junction with the p-type impurity region, lying in the first surface in contact with the shallow trench side face. An n+ source region makes a pn junction with the p-type region, lying in the first surface in contact with the side faces of deep and shallow trenches.
    Type: Application
    Filed: March 5, 2018
    Publication date: November 15, 2018
    Inventor: Kazuhisa MORI
  • Patent number: 7417487
    Abstract: An overheat detecting circuit according to an embodiment of the invention includes: a current source for generating a constant current; an overheat detecting element unit that operates with a first current generated in accordance with the constant current and generates a first voltage based on a semiconductor substrate temperature; and a detecting circuit unit that operates a second current generated in accordance with the constant current, and generates a second voltage corresponding to a predetermined semiconductor substrate temperature to detect overheating based on a voltage difference between the first voltage and a reference voltage and a voltage difference between the second voltage and the reference voltage.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: August 26, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Kazuhisa Mori
  • Patent number: 7239495
    Abstract: When the overcurrent detection circuit detects that a voltage drop of the output transistor exceeds a threshold value, it turns on the switch by the first operational amplifier. In the shut-down signal generation circuit, the capacitor is charged with a charge current determined based on a current depending on the voltage drop of the output transistor. The shut-down signal generation circuit generates a shut-down signal to turn off the output switch when a voltage of the capacitor exceeds a voltage of the inverting input terminal of the second operational amplifier.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Kazuhisa Mori, Ikuo Fukami
  • Publication number: 20060256494
    Abstract: An overheat detecting circuit according to an embodiment of the invention includes: a current source for generating a constant current; an overheat detecting element unit that operates with a first current generated in accordance with the constant current and generates a first voltage based on a semiconductor substrate temperature; and a detecting circuit unit that operates a second current generated in accordance with the constant current, and generates a second voltage corresponding to a predetermined semiconductor substrate temperature to detect overheating based on a voltage difference between the first voltage and a reference voltage and a voltage difference between the second voltage and the reference voltage.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 16, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kazuhisa Mori
  • Patent number: 7104363
    Abstract: An elevator having a power feeding apparatus effective for reducing the installation space for the elevator is disclosed. The dimension of the power transmission part disposed at the hoist way and the dimension of the power receiving part mounted on the counter weight, each measured in the direction along which the counter weight moves are made different from each other.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: September 12, 2006
    Inventors: Kazuhisa Mori, Kouki Yamamoto, Hideki Ayano, Ikuo Yamato, Hiromi Inaba, Hirokazu Nagura, Hideki Nihei
  • Patent number: 6891214
    Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Mori, Takashi Ikimi, Shuji Katoh, Yutaka Sato
  • Patent number: 6839213
    Abstract: A semiconductor power module capable of efficiently utilizing the performance of the module and facilitating management of the module in custody. The semiconductor power module having one or more semiconductor power switching elements and a drive unit is provided with a non-volatile memory for storing use history of the module and a drive unit. The use history contains information of one of the number of switching times of the semiconductor power switching element, the number of over-current detections of the semiconductor power switching element and a temperature rise of the semiconductor power module.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: January 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Mori, Takashi Ikimi, Shuji Katoh, Yutaka Sato
  • Publication number: 20040252434
    Abstract: When the overcurrent detection circuit detects that a voltage drop of the output transistor exceeds a threshold value, it turns on the switch by the first operational amplifier. In the shut-down signal generation circuit, the capacitor is charged with a charge current determined based on a current depending on the voltage drop of the output transistor. The shut-down signal generation circuit generates a shut-down signal to turn off the output switch when a voltage of the capacitor exceeds a voltage of the inverting input terminal of the second operational amplifier.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 16, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kazuhisa Mori, Ikuo Fukami