Patents by Inventor Kazuhito FURUMOTO

Kazuhito FURUMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11361966
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The second film includes fluoride of a first metal element having a first boiling point of 800° C. or higher and fluoride of a second metal element having a second boiling point of 800° C. or higher. The second metal element is different from the first metal element. The method further includes etching the first film using the second film as an etching mask and etching gas that includes fluorine.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 14, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Soichi Yamazaki, Kazuhito Furumoto, Kosuke Horibe, Keisuke Kikutani, Atsuko Sakata
  • Publication number: 20220045078
    Abstract: A method of manufacturing a semiconductor storage device includes forming a coating layer covering a base layer, forming a recess that penetrates the coating layer and into the base layer, enlarging a portion of the recess to expose a portion of the coating layer in contact with the base layer, and etching a surface of the coating layer exposed inside the recess.
    Type: Application
    Filed: March 3, 2021
    Publication date: February 10, 2022
    Inventor: Kazuhito FURUMOTO
  • Publication number: 20210020439
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The second film includes fluoride of a first metal element having a first boiling point of 800° C. or higher and fluoride of a second metal element having a second boiling point of 800° C. or higher. The second metal element is different from the first metal element. The method further includes etching the first film using the second film as an etching mask and etching gas that includes fluorine.
    Type: Application
    Filed: February 27, 2020
    Publication date: January 21, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Soichi YAMAZAKI, Kazuhito FURUMOTO, Kosuke HORIBE, Keisuke KIKUTANI, Atsuko SAKATA
  • Patent number: 10763122
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Yamazaki, Kazuhito Furumoto, Kosuke Horibe, Keisuke Kikutani, Atsuko Sakata, Junichi Wada, Toshiyuki Sasaki
  • Patent number: 10515797
    Abstract: According to one embodiment, a method for producing a semiconductor device includes forming a first film on a substrate. A second film is formed on the first film. A recess is formed in the second film. First processing by which a third film is formed on the second film to form a side face of the recess with the second film and second processing by which the first film exposed in the recess is processed by using the second and third films, are executed one or more times. In relation to an N-th (N is an integer greater than or equal to 1) first processing, before the third film is formed on the second film, a surface inclined with respect to the side face of the recess is formed above the side face of the recess.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhito Furumoto, Keisuke Kikutani, Soichi Yamazaki
  • Publication number: 20190259609
    Abstract: According to one embodiment, a method for producing a semiconductor device includes forming a first film on a substrate. A second film is formed on the first film. A recess is formed in the second film. First processing by which a third film is formed on the second film to form a side face of the recess with the second film and second processing by which the first film exposed in the recess is processed by using the second and third films, are executed one or more times. In relation to an N-th (N is an integer greater than or equal to 1) first processing, before the third film is formed on the second film, a surface inclined with respect to the side face of the recess is formed above the side face of the recess.
    Type: Application
    Filed: July 10, 2018
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhito FURUMOTO, Keisuke KIKUTANI, Soichi YAMAZAKI
  • Publication number: 20180261466
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi YAMAZAKI, Kazuhito FURUMOTO, Kosuke HORIBE, Keisuke KIKUTANI, Atsuko SAKATA, Junichi WADA, Toshiyuki SASAKI
  • Patent number: 9754888
    Abstract: A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, and a metal-containing layer provided at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films. The upper electrode film is in contact with the memory film.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhito Furumoto, Toshiyuki Sasaki
  • Patent number: 9741730
    Abstract: According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 22, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Murakoshi, Kazuhito Furumoto
  • Publication number: 20170170125
    Abstract: A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, and a metal-containing layer provided at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films. The upper electrode film is in contact with the memory film.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 15, 2017
    Inventors: Kazuhito FURUMOTO, Toshiyuki SASAKI
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Publication number: 20170077112
    Abstract: According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 16, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi MURAKOSHI, Kazuhito FURUMOTO
  • Publication number: 20160104718
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes etching an etching target layer under a mask layer using a first gas. The mask layer includes a plurality of first layers, one or more second layers, and a mask hole piercing through the plurality of first layers and the one or more second layers. The method includes etching an outermost first layer exposed to an outermost layer of the mask layer among the plurality of first layers using a second gas, and exposing a layer directly under the outermost first layer. The etching using the first gas and the etching using the second gas are repeated to form a hole in the etching target layer.
    Type: Application
    Filed: February 9, 2015
    Publication date: April 14, 2016
    Inventors: Mitsuhiro OMURA, Kazuhito Furumoto
  • Patent number: 9093261
    Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Sasaki, Mitsuhiro Omura, Kazuhito Furumoto
  • Publication number: 20150104942
    Abstract: A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus.
    Type: Application
    Filed: March 10, 2014
    Publication date: April 16, 2015
    Inventors: Toshiyuki SASAKI, Mitsuhiro OMURA, Kazuhito FURUMOTO