Patents by Inventor Kazuhito Nishitani

Kazuhito Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9666694
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 30, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhito Nishitani, Katsuhiro Sato
  • Publication number: 20150091075
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps.
    Type: Application
    Filed: September 4, 2014
    Publication date: April 2, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhito NISHITANI, Katsuhiro SATO
  • Patent number: 8569731
    Abstract: A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Konno, Hiroyuki Fukumizu, Kazuhito Nishitani
  • Patent number: 8274816
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory layer and a driver section. The memory layer has a first state having a first resistance under application of a first voltage, a second state having a second resistance higher than the first resistance under application of a second voltage higher than the first voltage, and a third state having a third resistance between the first resistance and the second resistance under application of a third voltage between the first voltage and the second voltage. The driver section is configured to apply at least one of the first voltage, the second voltage and the third voltage to the memory layer to record information in the memory layer.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: September 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriko Bota, Yasuhiro Nojiri, Hiroyuki Fukumizu, Takuya Konno, Kazuhito Nishitani
  • Patent number: 8153488
    Abstract: Manufacturing a nonvolatile storage device including: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a substrate; processing the first electrode film and the first storage unit film into a strip shape; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the sacrifice layer; forming a mask layer on the second electrode film; processing the second electrode film into a strip shape using the mask layer; removing a portion of the first storage unit film exposed from the sacrifice layer using the mask layer processing the first storage unit film into a columnar shape, removing the sacrifice layer exposing the first storage unit film; and removing the exposed first storage unit film.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhito Nishitani, Eiji Ito, Machiko Tsukiji, Hiroyuki Fukumizu, Naoya Hayamizu, Katsuhiro Sato
  • Publication number: 20110149638
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory layer and a driver section. The memory layer has a first state having a first resistance under application of a first voltage, a second state having a second resistance higher than the first resistance under application of a second voltage higher than the first voltage, and a third state having a third resistance between the first resistance and the second resistance under application of a third voltage between the first voltage and the second voltage. The driver section is configured to apply at least one of the first voltage, the second voltage and the third voltage to the memory layer to record information in the memory layer.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noriko BOTA, Yasuhiro Nojiri, Hiroyuki Fukumizu, Takuya Konno, Kazuhito Nishitani
  • Publication number: 20100244114
    Abstract: A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuya Konno, Hiroyuki Fukumizu, Kazuhito Nishitani
  • Publication number: 20100248431
    Abstract: A method for manufacturing a nonvolatile storage device including: a plurality of first electrodes aligning in a first direction; a plurality of second electrodes aligning in a second direction nonparallel to the first direction and provided above the first electrodes; and a first storage unit provided between the first electrode and the second electrode and including a first storage layer, a resistance of the first storage layer changing by at least one of an applied electric field and an applied current, the method includes: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a major surface of a substrate; processing the first electrode film and the first storage unit film into a strip shape aligning in the first direction; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito NISHITANI, Eiji Ito, Machiko Tsukiji, Hiroyuki Fukumizu, Naoya Hayamizu, Katsuhiro Sato
  • Publication number: 20080073699
    Abstract: A method for manufacturing a semiconductor device includes: forming a first film on a base body; crystallizing the first film by heating; thinning the crystallized first film; and forming a second film on the thinned first film. The first film is made of a material having a high dielectric constant than silicon oxide. A semiconductor device includes: a silicon substrate; a tunnel insulating film provided on the silicon substrate; a floating gate electrode provided on the tunnel insulating film; a polycrystalline insulating film provided on the floating gate electrode; and a control gate electrode provided on the polycrystalline insulating film.
    Type: Application
    Filed: March 21, 2007
    Publication date: March 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito Nishitani, Hidehiko Yabuhara