Abstract: First compensation circuitry includes a first digital filter compensating a phase difference between a phase of a symbol of a received signal and a sampling timing, and first filter coefficient calculation circuitry calculating a filter coefficient of the first digital filter as a first filter coefficient. Second filter coefficient calculation circuitry calculates, as a second filter coefficient, a filter coefficient for adaptive equalization that compensates distortion due to temporally changing polarization dispersion, based on an output of the first digital filter. Coefficient combination circuitry combines the first filter coefficient and the second filter coefficient. Second compensation circuitry includes a second digital filter which uses a filter coefficient combined by the coefficient combination circuitry and performs a compensation of the phase difference between the phase of the symbol of the received signal and the sampling timing, and a process of the adaptive equalization at the same time.

Abstract: An arithmetic circuit includes a LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: First compensation circuitry includes a first digital filter compensating a phase difference between a phase of a symbol of a received signal and a sampling timing, and first filter coefficient calculation circuitry calculating a filter coefficient of the first digital filter as a first filter coefficient. Second filter coefficient calculation circuitry calculates, as a second filter coefficient, a filter coefficient for adaptive equalization that compensates distortion due to temporally changing polarization dispersion, based on an output of the first digital filter. Coefficient combination circuitry combines the first filter coefficient and the second filter coefficient. Second compensation circuitry includes a second digital filter which uses a filter coefficient combined by the coefficient combination circuitry and performs a compensation of the phase difference between the phase of the symbol of the received signal and the sampling timing, and a process of the adaptive equalization at the same time.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] are multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: A processing equipment includes a processing unit having a plurality of functions. A retaining unit retains a device identifier capable of identifying the processing equipment. An interface unit receives a function authentication key which is a code for setting a specific function among the plurality of functions to be enabled or disabled. A control unit sets the specific function to be enabled or disabled according to the function authentication key when a device identifier included in the received function authentication key coincides with the device identifier retained in the retaining unit.

Abstract: A reception circuit includes a first adaptive compensator compensating distortion of a received signal. An adaptive compensation coefficient calculator includes a known-signal detector detecting first and second known-signals from the received signal, a second adaptive compensator compensating distortion of the received signal, a tap coefficient initial value calculator calculating an initial value of a tap coefficient of the second adaptive compensator by comparing the first known-signal with its true value, a first phase shift compensator compensating phase shift of an output of the second adaptive compensator using the second known-signal, and a tap coefficient calculator calculating tap coefficients of the first and second adaptive compensators by comparing at least one of the first and second known-signals compensated by the second adaptive compensator and the first phase shift compensator with its true value.

Abstract: A symbol phase difference compensating portion (6) calculates a first phase difference which is a phase difference between a known pattern extracted from a received signal and a true value of the known pattern and performs phase compensation for the received signal based on the first phase difference. A tentative determination portion (12) tentatively determines an output signal of the symbol phase difference compensating portion (6) to acquire an estimated value of a phase. A first phase difference acquiring portion (13) acquires a second phase difference which is a phase difference between a phase of the output signal and the estimated value of the phase acquired by the tentative determination portion (12). A first phase difference compensating portion (14) performs phase compensation for the output signal based on the second phase difference.

Abstract: An I component compensation unit calculates an I component in which a distortion has been compensated, by forming a first polynomial expressing the distortion of the I component based on an I component and a Q component of a quadrature modulation signal and multiplying each term of the first polynomial by a first coefficient. A Q component compensation unit calculates a Q component in which a distortion has been compensated, by forming a second polynomial expressing the distortion of the Q component based on the I component and the Q component of the quadrature modulation signal and multiplying each term of the second polynomial by a second coefficient. A coefficient calculation unit calculates the first and second coefficients by comparing outputs of the I component compensation unit and the Q component compensation unit and a known signal.

Abstract: An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

Abstract: An I component compensation unit calculates an I component in which a distortion has been compensated, by forming a first polynomial expressing the distortion of the I component based on an I component and a Q component of a quadrature modulation signal and multiplying each term of the first polynomial by a first coefficient. A Q component compensation unit calculates a Q component in which a distortion has been compensated, by forming a second polynomial expressing the distortion of the Q component based on the I component and the Q component of the quadrature modulation signal and multiplying each term of the second polynomial by a second coefficient. A coefficient calculation unit calculates the first and second coefficients by comparing outputs of the I component compensation unit and the Q component compensation unit and a known signal.

Abstract: A symbol phase difference compensating portion (6) calculates a first phase difference which is a phase difference between a known pattern extracted from a received signal and a true value of the known pattern and performs phase compensation for the received signal based on the first phase difference. A tentative determination portion (12) tentatively determines an output signal of the symbol phase difference compensating portion (6) to acquire an estimated value of a phase. A first phase difference acquiring portion (13) acquires a second phase difference which is a phase difference between a phase of the output signal and the estimated value of the phase acquired by the tentative determination portion (12). A first phase difference compensating portion (14) performs phase compensation for the output signal based on the second phase difference.

Abstract: A reception circuit includes a first adaptive compensator compensating distortion of a received signal. An adaptive compensation coefficient calculator includes a known-signal detector detecting first and second known-signals from the received signal, a second adaptive compensator compensating distortion of the received signal, a tap coefficient initial value calculator calculating an initial value of a tap coefficient of the second adaptive compensator by comparing the first known-signal with its true value, a first phase shift compensator compensating phase shift of an output of the second adaptive compensator using the second known-signal, and a tap coefficient calculator calculating tap coefficients of the first and second adaptive compensators by comparing at least one of the first and second known-signals compensated by the second adaptive compensator and the first phase shift compensator with its true value.

Abstract: A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

Abstract: Signal processing sections selectively switch modulation/demodulation in low-efficiency modulation system and modulation/demodulation in high-efficiency modulation system, and perform digital signal processing. Parallel-side interfaces of input/output interface sections are electrically connected to the signal processing section. A serial-side interface of the input/output interface section is electrically connected to a serial-side interface of the input/output interface section. A selection section electrically connects a parallel-side interface of the input/output interface section to the signal processing section when the low-efficiency modulation system is selected, and electrically connects the parallel-side interface of the input/output interface section to a parallel-side interface of the input/output interface section when the high-efficiency modulation system is selected.

Abstract: An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

Abstract: A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

Abstract: Signal processing sections selectively switch modulation/demodulation in low-efficiency modulation system and modulation/demodulation in high-efficiency modulation system, and perform digital signal processing. Parallel-side interfaces of input/output interface sections are electrically connected to the signal processing section. A serial-side interface of the input/output interface section is electrically connected to a serial-side interface of the input/output interface section. A selection section electrically connects a parallel-side interface of the input/output interface section to the signal processing section when the low-efficiency modulation system is selected, and electrically connects the parallel-side interface of the input/output interface section to a parallel-side interface of the input/output interface section when the high-efficiency modulation system is selected.