Abstract: There is disclosed a start-up circuit (3a) wherein a plurality of NMOSs (Q8 to Q10) are connected in series between the drain of a PMOS (Q1) and a ground potential point (2) and connected at their gate to a power-supply potential point (1), and wherein a voltage drop at the NMOSs (Q8 to Q10) generates a gate potential of a PMOS (Q2) for supplying current to a bias supply circuit (4). By using the voltage drop of the NMOSs (Q8 to Q10) having a small area, the start-up circuit including a CMOS is reduced in layout area.

Abstract: Anode and cathode regions at a principal surface of a semiconductor substrate have the same characteristics as source and drain regions of a P type MOS transistor. A cathode region is superposed partially on the anode region at the principal surface of the semiconductor substrate, the cathode region having the same characteristics as source and drain regions of an N type MOS transistor. The cathode and anode regions form a Zener diode. The Zener diode may be short-circuited by a large current flow, i.e., zapping, or used as a voltage regulator.

Abstract: A test circuit for testing a current-voltage conversion amplifier having photodiode (PD) without actually exposing light to PD, including a current mirror circuit having a first NPN transistor and a second NPN transistor, an input terminal for applying a test voltage, a resistor connected between the input terminal and a collector of the first NPN transistor, and a current terminal connected to a collector of the second NPN transistor. The test circuit passes a current from the current-voltage conversion amplifier to the current terminal according to the test voltage which is applied to the input terminal.

Abstract: A CMOS circuit (7) receives the potentials V.sub.CC and V.sub.EE1 from potential points (50 and 52), respectively, to apply an output to the gate of a transistor (3a). The drain of the transistor (3a) is connected through a resistor (4) to a potential point (53) providing the potential V.sub.EE2. The gate of a transistor 6, along with the drain of the transistor (3a), is connected through the resistor (4) to the potential point (53). The gate of a transistor (5) is connected to an input terminal (IN). In this circuit configuration, the time constant of potential drop toward the potential V.sub.EE2 at the gate of the transistor (6) through the resistor (4) is smaller because the gate capacitance of the transistor (5) does not relate thereto, so that a quick potential drop at the gate of the transistor (6) can be achieved.