Patents by Inventor Kazuhito Yumoto

Kazuhito Yumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268712
    Abstract: A method of manufacturing a semiconductor device includes: preparing a bottom plate having an upper surface and a lower surface, wherein the lower surface of the bottom plate comprises a reference part and one or more inclined surfaces that are inclined with respect to the reference part, an upper portion of the one or more inclined surfaces being positioned above the reference part, and wherein a thickness of the bottom plate at the reference part is greater than a thickness of the bottom plate at the upper portion of the one or more inclined surfaces; joining a frame member to the bottom plate, at least a part of the frame member being disposed directly above the one or more inclined surfaces, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate; and fixing a semiconductor element to the bottom plate.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Applicants: NICHIA CORPORATION, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takuya Hashimoto, Eiichiro Okahisa, Katsuya Nakazawa, Shigeru Matsushita, Sumio Uehara, Suguru Kobayashi, Kazuhito Yumoto
  • Patent number: 11677211
    Abstract: A semiconductor device includes: a bottom plate having an upper surface and a lower surface, wherein the upper surface comprises an outer peripheral part and an inside part that is enclosed by the outer peripheral part and that protrudes more upward than the outer peripheral part; a frame joined to the upper surface of the bottom plate and comprising a first through-hole that penetrates the frame; a plate jointed to the outside or inside surface of the frame, the plate comprising a second through-hole that penetrates the plate in a same direction as that of the first through-hole, a thickness of the plate being greater than a thickness of the frame; a lead terminal inserted into the first through-hole and the second through-hole; a fixing member provided in the second through-hole and fixing the lead terminal; and a semiconductor element fixed to the inside part.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: June 13, 2023
    Assignees: NICHIA CORPORATION, SHINIKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takuya Hashimoto, Eiichiro Okahisa, Katsuya Nakazawa, Shigeru Matsushita, Sumio Uehara, Suguru Kobayashi, Kazuhito Yumoto
  • Publication number: 20210021097
    Abstract: A semiconductor device includes: a bottom plate having an upper surface and a lower surface, wherein the upper surface comprises an outer peripheral part and an inside part that is enclosed by the outer peripheral part and that protrudes more upward than the outer peripheral part; a frame joined to the upper surface of the bottom plate and comprising a first through-hole that penetrates the frame; a plate jointed to the outside or inside surface of the frame, the plate comprising a second through-hole that penetrates the plate in a same direction as that of the first through-hole, a thickness of the plate being greater than a thickness of the frame; a lead terminal inserted into the first through-hole and the second through-hole; a fixing member provided in the second through-hole and fixing the lead terminal; and a semiconductor element fixed to the inside part.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Applicants: NICHIA CORPORATION, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takuya Hashimoto, Eiichiro Okahisa, Katsuya Nakazawa, Shigeru Matsushita, Sumio Uehara, Suguru Kobayashi, Kazuhito Yumoto
  • Patent number: 10833473
    Abstract: A method of manufacturing a semiconductor device includes, in this order: preparing a bottom plate having an upper surface and a lower surface, wherein the upper surface includes an outer peripheral part and an inside part that is enclosed by the outer peripheral part and that protrudes more upward than the outer peripheral part, and wherein the lower surface of the bottom plate includes a reference part and a recess positioned above the reference part, at least a part of the recess being disposed directly below the outer peripheral part; joining a frame member to the outer peripheral part of the bottom plate, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate; and fixing a semiconductor element to the inside part of the bottom plate.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 10, 2020
    Assignees: NICHIA CORPORATION, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takuya Hashimoto, Eiichiro Okahisa, Katsuya Nakazawa, Shigeru Matsushita, Sumio Uehara, Suguru Kobayashi, Kazuhito Yumoto
  • Publication number: 20190305511
    Abstract: A method of manufacturing a semiconductor device includes, in this order: preparing a bottom plate having an upper surface and a lower surface, wherein the upper surface includes an outer peripheral part and an inside part that is enclosed by the outer peripheral part and that protrudes more upward than the outer peripheral part, and wherein the lower surface of the bottom plate includes a reference part and a recess positioned above the reference part, at least a part of the recess being disposed directly below the outer peripheral part; joining a frame member to the outer peripheral part of the bottom plate, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate; and fixing a semiconductor element to the inside part of the bottom plate.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 3, 2019
    Applicants: NICHIA CORPORATION, SHINKO ELECTONIC INDUSTRIES CO., LTD.
    Inventors: Takuya Hashimoto, Eiichiro Okahisa, Katsuya Nakazawa, Shigeru Matsushita, Sumio Uehara, Suguru Kobayashi, Kazuhito Yumoto
  • Patent number: 5859471
    Abstract: In a lead frame adapted to be used for a semiconductor device, a plurality of inner leads are made of a thin conductive material for easily forming a fine pattern of the inner leads. A plurality of outer leads are integrally formed with the respective inner leads. The outer leads are coated with metal layers to increase the thickness thereof, so that a desired strength of the outer leads is obtained. A semiconductor chip is electrically connected to the inner leads. The semiconductor chip and a part of the lead frame including the inner leads are hermetically sealed with a resin and, thus, a semiconductor device is obtained.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: January 12, 1999
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Fumio Kuraishi, Kazuhito Yumoto, Mamoru Hayashi
  • Patent number: 5384204
    Abstract: A tape useful for an automatic bonding process when manufacturing a high-frequency semiconductor device, the tape comprising an insulating flexible film, and circuit patterns consisting of copper or copper-alloy formed on the insulating film, each of the circuit patterns having inner and an outer lead portions. A tin or tin-lead plated film is formed on the pattern, and an intermediate plated film is formed on at least the outer lead portion as an underlayer. The intermediate plated film consists of a metal or metal alloy selected from nickel, cobalt, gold, silver, platinum, palladium, indium or rhodium.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: January 24, 1995
    Assignee: Shinko Electric Industries Co. Ltd.
    Inventors: Kazuhito Yumoto, Norio Wakabayashi, Masao Nakazawa, Shinichi Wakabayashi, Norio Wada, Fumio Kuraishi, Toshihiko Shimada