Patents by Inventor Kazuki Sakuma

Kazuki Sakuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112475
    Abstract: A looking away determination device includes: a determination unit that determines that a driver is in a looking away state when a proportion of an image in which a face of the driver is not detected with respect to a plurality of images obtained by imaging the driver is equal to or greater than a first predetermined value, the first predetermined value being determined based on driving state information that indicates a state during driving by the driver.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Applicant: NEC Corporation
    Inventors: Kazuki INAGAKI, Nana SAKUMA
  • Publication number: 20240083443
    Abstract: A driving-state monitoring system includes a driving-state monitoring device and a driving-state sensing device. The driving-state sensing device captures an image of a driver of a vehicle to thereby generate driving-state data. The driving-state monitoring device acquires the driving-state data and the captured image of a driver of a vehicle from the driving-state sensing device. An authentication process is made to determine whether or not a driver matches a pre-registered driver based on the information of a driver included in the captured image, thus determining the identification information of the driver successfully authenticated. The driving-state data is recorded on a database in association with the identification information of the driver. Accordingly, it is possible for the driving-state monitoring device to monitor a plurality of vehicles using a plurality of driving-state sensing devices, thus precisely managing a plurality of vehicles in terms of their driving states.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: NEC Corporation
    Inventors: Kazuki INAGAKI, Hidenori Tsukahara, Nana Sakuma, Kazuki Ogata
  • Publication number: 20210297430
    Abstract: A vehicle control apparatus includes: a steering control unit connected to an in-vehicle communication network mounted on a vehicle and configured to control a steering motor configured to add an auxiliary torque corresponding to a steering operation by a driver to a steering mechanism; and an illegal signal detection unit connected to the in-vehicle communication network and configured to detect an illegal signal input to the in-vehicle communication network. The steering control unit restricts the auxiliary torque when the illegal signal is detected by the illegal signal detection unit.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 23, 2021
    Inventors: Ryosuke Oguchi, Yoshiyuki Amanuma, Kensuke Yamamoto, Ryoji Nishimoto, Kazuki Sakuma
  • Patent number: 9053821
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 9, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Publication number: 20140211582
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Patent number: 8737149
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 27, 2014
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Publication number: 20120127814
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 24, 2012
    Inventors: Yoshiro RIHO, Hiromasa NODA, Kazuki SAKUMA
  • Publication number: 20080151659
    Abstract: A semiconductor memory device includes at least one memory bank. Each memory bank includes: memory units that output data in response to a burst read command; a selector section that sequentially outputs the data output from the memory units in accordance with a select signal; a comparator section that compares the data sequentially output from the selector section with reference data sequentially input, outputs a comparison result indicating normal when the data output from the selector section matches with the reference data, and outputs a comparison result indicating abnormal when the data output from the selector section does not match with the reference data; and a reduction result storage section that stores, as a reduction result of the memory bank, a value indicating normal when comparison results sequentially output from the comparator section all indicate normal, and a value indicating abnormal when any one of the comparison results indicates abnormal.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 26, 2008
    Applicant: Elpida Memory Inc.
    Inventors: Kazuki Sakuma, Jun Suzuki, Chiaki Dono
  • Patent number: 7227251
    Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: June 5, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
  • Publication number: 20050184380
    Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
    Type: Application
    Filed: April 26, 2005
    Publication date: August 25, 2005
    Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
  • Patent number: 6885092
    Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: April 26, 2005
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano