Abstract: In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.

Abstract: In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.

Abstract: A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array. In the memory cell array, a memory cell length in the first direction is substantially n times the transistor pitch, wherein n is an integer.

Abstract: A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.

Abstract: Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.

Abstract: Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.

Abstract: An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.

Abstract: A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.

Abstract: A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.

Abstract: An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.

Abstract: A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.

Abstract: A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.

Abstract: A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.