Patents by Inventor Kazuma Yoshida
Kazuma Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715795Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: GrantFiled: October 5, 2021Date of Patent: August 1, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: 11626399Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: February 1, 2022Date of Patent: April 11, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
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Patent number: 11495799Abstract: To provide a negative electrode of a lithium ion battery excellent in cycle life characteristics. The negative electrode for a lithium ion battery includes an Si-based material as an active material, wherein a skeleton-forming agent including a silicate having a siloxane bond or a phosphate having an aluminophosphate bond as an ingredient is present on the surface and inside of an active material layer, and the skeleton of the active material is formed with the skeleton-forming agent.Type: GrantFiled: March 25, 2017Date of Patent: November 8, 2022Assignee: ATTACCATO LIMIIED LIABILITY COMPANYInventors: Taichi Sakamoto, Takashi Mukai, Yuta Ikeuchi, Naoto Yamashita, Daichi Iwanari, Kazuma Yoshida, Kazuyoshi Tanaka
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Publication number: 20220157806Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Kazuma YOSHIDA, Ryosuke Okawa, Tsubasa Inoue
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Patent number: 11282834Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: April 12, 2021Date of Patent: March 22, 2022Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
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Publication number: 20220029016Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Ryosuke OKAWA, Toshikazu IMAI, Kazuma YOSHIDA, Tsubasa INOUE, Takeshi IMAMURA
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Patent number: 11171234Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: GrantFiled: August 6, 2020Date of Patent: November 9, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Publication number: 20210233905Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Kazuma Yoshida, Ryosuke OKAWA, Tsubasa INOUE
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Patent number: 11069783Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: GrantFiled: October 20, 2020Date of Patent: July 20, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
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Patent number: 11056589Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: GrantFiled: October 14, 2020Date of Patent: July 6, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
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Patent number: 11056563Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: GrantFiled: October 20, 2020Date of Patent: July 6, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
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Patent number: 11049856Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: January 25, 2019Date of Patent: June 29, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
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Patent number: D934820Type: GrantFiled: October 24, 2019Date of Patent: November 2, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: D937232Type: GrantFiled: July 30, 2021Date of Patent: November 30, 2021Assignee: Nuvoton Technology Corporation JapanInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: D937233Type: GrantFiled: July 30, 2021Date of Patent: November 30, 2021Assignee: Nuvoton Technology Corporation JapanInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: D938925Type: GrantFiled: October 24, 2019Date of Patent: December 21, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: D951212Type: GrantFiled: May 12, 2020Date of Patent: May 10, 2022Assignee: Panasonic Semiconductor Solutions Co., Ltd.Inventors: Takeshi Imamura, Kazuma Yoshida, Ryosuke Okawa, Toshikazu Imai
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Patent number: D951213Type: GrantFiled: May 12, 2020Date of Patent: May 10, 2022Assignee: Panasonic Semiconductor Solutions Co., Ltd.Inventors: Takeshi Imamura, Kazuma Yoshida, Ryosuke Okawa, Toshikazu Imai
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Patent number: D951214Type: GrantFiled: May 12, 2020Date of Patent: May 10, 2022Assignee: Panasonic Semiconductor Solutions Co., Ltd.Inventors: Takeshi Imamura, Kazuma Yoshida, Ryosuke Okawa, Toshikazu Imai
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Patent number: D951215Type: GrantFiled: May 12, 2020Date of Patent: May 10, 2022Assignee: Panasonic Semiconductor Solutions Co., Ltd.Inventors: Takeshi Imamura, Kazuma Yoshida, Ryosuke Okawa, Toshikazu Imai