Abstract: In a data processing system where a plurality of nodes, each having a plurality of processors and cache memories associated with each of the processors, are connected via a bus, tag information is added to each data block stored in the cache memories. The tag information has state information which includes information (INTERNODE-SHARED) indicative of whether or not the data block is cached in another node. When a write-access is transmitted to the data block in the cache memory, if the state information added to the data block is INTERNODE-SHARED, invalidation of the data block is requested to the other node.

Abstract: In a system in which a plurality of nodes are connected using a light wavelength multiplexing connection route which can simultaneously connect nodes using light beams of a plurality of different wavelengths, each node has a cache memory for holding data in memories in other nodes. Some or all of the pieces of information required for data transfer in one node or between the nodes are transferred from the node to an arbiter used in use arbitration of the connection route via one of arbitration optical signal routes for respectively connecting the arbiter and the nodes. The arbiter distributes the transferred information to other nodes, and each node updates the contents of its cache memory on the basis of the distributed information.

Abstract: An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY block in the cache memory is started. The cache memory issues a bus transaction onto a system bus and performs write back of the DIRTY block in the cache memory relative to a main memory. The write back bus transaction issued from the cache memory in the foregoing fashion is snooped by the other cache memory. With this arrangement, an unnecessary consistency holding operation can be omitted to reduce a delay upon memory accessing in a parallel computer system employing a loose memory consistency model.

Abstract: An information processing apparatus has a plurality of nodes, a connection line for connection between the plurality of nodes, an arbiter for performing arbitration of use of the connection line, and an arbitration signal line for connection between the arbiter and each node, wherein the arbiter performs processing of a request for use of the connection line and processing of additional information related to data transfer executed after connection of the connection line.

Abstract: An information processing apparatus in which continuous data of a plurality of series in which the contents of the data of each series are related to each other with respect to time is pipeline processed by a data processing system. The apparatus comprises a plurality of sync generation circuits which correspond to the plurality of series and each of which generate sync signals to instruct timings for the data transfer and data process of each series, and a sync control circuit for controlling generation situations of the sync signals from the plurality of sync generation circuits in accordance with a degree of progress of the data process of each series in the data processing system so that the data of each series can be processed in the data processing system without losing the time-dependent relation.

Abstract: An information processing system has a plurality of nodes each including one or more CPUs that utilize monitoring of a common bus, wherein the plurality of nodes are connected to one another by a connection path that cannot monitor information on an internal bus in each node. Information required to perform synchronized operation in a node or among nodes is transmitted to an arbiter via an optical fiber serving as a transmission path different from the connection path, and part of this information is again distributed from the arbiter to each of the nodes based upon the information. The system operates in such a manner that the information is reflected in its own node based upon the re-distributed information. Further, in order to perform the synchronized operation among CPUs based upon the re-distributed information, the system controls the information to be distributed from each node to arbiter.

Abstract: An information processing apparatus which processes a large amount of data at high speed. The synchronizing signal has a cycle including a transfer period and a processing period. In the transfer period, data is transferred, e.g., from a data input unit to a first memory, and from the first memory to a second memory. In the processing period, the data input unit reads data for one frame of a digital video image, and a data output unit displays an image based on the image data. Processors respectively perform predetermined processing upon data stored in a memory connected to the processor. Thus, within one cycle of the synchronizing signal, processing is completed at respective stages from input to output. Note that the connection between the memories and the processors may be changed for performing the processing at the respective stages without data transfer. In this case, data transfer time can be saved.

Abstract: When a synchronization point is determined to maintain the coherence of data in a multi-processor system, and data write-back operations from caches to a main memory are simultaneously performed at the determined point, the traffic is concentrated, resulting in poor efficiency. In view of this problem, the write-back operations of cache data are arbitrarily performed when a predetermined condition is satisfied. Alternatively, when the number of copies which are updated in the cache and do not match the corresponding data in the main memory exceeds a predetermined value, cache data are written back. With this control, the write-back operations of copies stored in cache can be prevented from being concentrated at the synchronization point.

Abstract: An information processing method and a system therefor are capable of performing a synchronized operation among CPUs over nodes that cannot monitor each other's internal buses. The system has a plurality of nodes each including one or more CPUs that use monitoring of a common internal bus as a mechanism for synchronizing the CPUs, wherein the plurality of nodes are connected to one another by a connection path that cannot monitor information in a bus in each node. The information processing system includes a transmitter for transmitting information required to perform a synchronized operation in the node or among the nodes through the connection path, and a reflector for reflecting a portion or the overall body of information to the node in accordance with information transmitted by the transmitter so that synchronization of operations of the CPUs over the nodes is realized.

Abstract: In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".

Abstract: An information processing apparatus transmits data among a plurality of nodes connected to a common transmission line. An arbiter selectively gives use permission, to use the common transmission line for transmitting data, to one of the nodes that requests the use permission on the basis of at least a use request therefor. A data transmission state detector detects the data transmission state on the common transmission line by monitoring for a separate signal on the common transmission line, and notifies the detected state to the arbiter. The arbiter then can use the detected state to give use permission to a requesting node, for example when plural requests are overlappingly received. Advantageously, the separate signal is either an identifier which was added to data and indicates an end of that data, or an identifier that indicates that a current data transmission will be finished after the lapse of a predetermined time.

Abstract: An information processing apparatus has a plurality of computational nodes including a multiplexer and a demultiplexer. A concentrator is connected to the nodes and simultaneously transmits multiplexed signals thereto. An arbiter arbitrates the use of a transmission line for data transfer, with the arbitration and data transfer signals being multiplexed.

Abstract: In a system having a memory unit using a memory for a block transfer function, access requested from a processor is executed by using the block transfer function even if the requested access is not block access to be conducted with respect to a block, provided that block transfer is possible.

Abstract: In an optical communication system, a plurality of apparatuses are connected by a star coupler. A signal from each of the optical communication apparatuses is received by a receiving device such as a photodiode while a signal to each of the apparatuses is transmitted by a transmitting device such as a laser diode. A reference clock is supplied to the transmitting device. A clock of the signal from an optical communication apparatus is extracted to generate a phase comparison information signal of the extracted clock and the reference clock so as to supply the phase comparison information signal to the transmitting device.

Abstract: A block substitution method of a cache memory incudes the steps of storing data integrity information with a main memory for each block of the cache memory and calculating a non-reference period of each block. The non-reference periods of the blocks are compared to determine an order of the blocks based on the non-reference periods and a difference between the non-reference period of the block having a longest non-reference period and the non-reference period of other blocks is calculated. Data integrity in the block having the longest non-reference period is examined and when there is no data integrity in that block the data integrity in other blocks is examined in the order of the non-reference period. A block having a longest non-reference period among the blocks having the data integrity is determined and the determined block is selected as a block to be substituted by a new data block when the difference is smaller than a predetermined value. New data is loaded to the selected block.

Abstract: This disclosure relates to a terminal unit for processing voice information which is adopted in a network system for transmitting and receiving voice information. This disclosure also pertains to a group of such terminal units. In a case where a voice converter is not provided in the terminal unit or when the use of the voice converter is suppressed, the terminal unit converts received voice information into a medium other than voice, for example, into characters, and thereby conveys it to a receiver. In a case where the terminal unit which receives the voice information is not provided with the function of converting the received voice information into a medium other than voice, the terminal unit requests another terminal unit within the terminal unit group to convert the voice information into a medium other than voice and thereby conveys it to a receiver.

Abstract: In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.