Patents by Inventor Kazumi Ikeda
Kazumi Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120288052Abstract: A nuclear reactor includes a reflector and a flow path. The reflector reflects neutrons, contains graphite and a moderator having a smaller moderating power than the graphite, and is sectioned into plural parts along a direction of flow of fuel pebbles. The flow path is surrounded by the reflector, and the fuel pebbles flow through the flow path and undergo nuclear reaction to generate power. Volume ratio of the graphite to the moderator having a smaller moderating power than the graphite in each part of the reflector is determined based on a power distribution in the reactor core in the direction of flow of the fuel pebbles.Type: ApplicationFiled: July 27, 2012Publication date: November 15, 2012Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kazumi Ikeda, Taro Kan
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Publication number: 20110222641Abstract: A nuclear reactor includes a reflector and a flow path. The reflector reflects neutrons, contains graphite and a moderator having a smaller moderating power than the graphite, and is sectioned into plural parts along a direction of flow of fuel pebbles. The flow path is surrounded by the reflector, and the fuel pebbles flow through the flow path and undergo nuclear reaction to generate power. Volume ratio of the graphite to the moderator having a smaller moderating power than the graphite in each part of the reflector is determined based on a power distribution in the reactor core in the direction of flow of the fuel pebbles.Type: ApplicationFiled: May 25, 2011Publication date: September 15, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kazumi Ikeda, Taro Kan
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Patent number: 7978807Abstract: A nuclear reactor includes a reflector and a flow path. The reflector reflects neutrons, contains graphite and a moderator having a smaller moderating power than the graphite, and is sectioned into plural parts along a direction of flow of fuel pebbles. The flow path is surrounded by the reflector, and the fuel pebbles flow through the flow path and undergo nuclear reaction to generate power. Volume ratio of the graphite to the moderator having a smaller moderating power than the graphite in each part of the reflector is determined based on a power distribution in the reactor core in the direction of flow of the fuel pebbles.Type: GrantFiled: December 27, 2007Date of Patent: July 12, 2011Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Kazumi Ikeda, Taro Kan
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Publication number: 20110142190Abstract: A nuclear reactor includes a reflector and a flow path. The reflector reflects neutrons, contains graphite and a moderator having a smaller moderating power than the graphite, and is sectioned into plural parts along a direction of flow of fuel pebbles. The flow path is surrounded by the reflector, and the fuel pebbles flow through the flow path and undergo nuclear reaction to generate power. Volume ratio of the graphite to the moderator having a smaller moderating power than the graphite in each part of the reflector is determined based on a power distribution in the reactor core in the direction of flow of the fuel pebbles.Type: ApplicationFiled: December 27, 2007Publication date: June 16, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kazumi IKEDA, Taro KAN
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Patent number: 7426662Abstract: A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.Type: GrantFiled: March 14, 2005Date of Patent: September 16, 2008Assignee: Hitachi, Ltd.Inventors: Tomoki Sekiguchi, Toshiaki Arai, Hiroshi Furukawa, Kazumi Ikeda
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Patent number: 6948100Abstract: A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.Type: GrantFiled: February 24, 1999Date of Patent: September 20, 2005Assignee: Hitachi, Ltd.Inventors: Tomoki Sekiguchi, Toshiaki Arai, Hiroshi Furukawa, Kazumi Ikeda
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Patent number: 6937480Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.Type: GrantFiled: May 10, 2002Date of Patent: August 30, 2005Assignee: Fuji Xerox Co., Ltd.Inventors: Daisuke Iguchi, Joji Wakita, Kazumi Ikeda, Osamu Ueno
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Publication number: 20050172169Abstract: A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Inventors: Tomoki Sekiguchi, Toshiaki Arai, Hiroshi Furukawa, Kazumi Ikeda
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Publication number: 20020176236Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer-connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.Type: ApplicationFiled: May 10, 2002Publication date: November 28, 2002Applicant: FUJI XEROX CO., LTD.Inventors: Daisuke Iguchi, Joji Wakita, Kazumi Ikeda, Osamu Ueno
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Patent number: 6431961Abstract: A grindstone and a wafer are rotated at high speeds in the same direction. The rotating wafer is slowly moved toward the rotating grindstone to thereby gradually chamfer the periphery of the wafer.Type: GrantFiled: February 23, 2000Date of Patent: August 13, 2002Assignee: Tokyo Seimitsu Co., Ltd.Inventors: Ichiro Katayama, Masatami Iwaki, Kazumi Ikeda
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Patent number: 6267648Abstract: A grindstone and a wafer are rotated at high speeds in the same direction. The rotating wafer is slowly moved toward the rotating grindstone to thereby gradually chamfer the periphery of the wafer.Type: GrantFiled: May 14, 1999Date of Patent: July 31, 2001Assignee: Tokyo Seimitsu Co. Ltd.Inventors: Ichiro Katayama, Masatami Iwaki, Kazumi Ikeda
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Patent number: 6066031Abstract: A wafer to be chamfered is supported in such a manner as to rotate and to move in the X-axis direction and the Y-axis direction which are perpendicular to one another, and a periphery grinding wheel is rotatably placed on the Y-axis. To chamfer a circular part of the wafer, the circular part of the wafer is pressed against the rotating periphery grinding wheel, and then, the wafer is rotated. To chamfer an orientation flat of the wafer, the orientation flat of the wafer is pressed against the rotating periphery grinding wheel, and then, the wafer is fed in the X-axis direction.Type: GrantFiled: March 9, 1998Date of Patent: May 23, 2000Assignee: Tokyo Seimitsu Co., Ltd.Inventors: Etsuo Noguchi, Kazumi Ikeda
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Patent number: 6062953Abstract: The peripheral edge of a wafer is cramped by four cramp rollers which are able to move forward and backward with respect to a reference point, and thereby, the center of the wafer is positioned at the reference point. Then, a notch pin, which is provided on a reference line, is pressed against the peripheral edge of the wafer, and the wafer is rotated about the reference point. Thereby, a notch on the wafer moves to the notch pin, and then, the notch pin fits into the notch. Thus, the wafer is positioned at a predetermined position.Type: GrantFiled: March 17, 1998Date of Patent: May 16, 2000Assignee: Tokyo Seimitsu Co., Ltd.Inventors: Jun Takaya, Kazumi Ikeda