Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.

Abstract: A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.

Abstract: A multi-way interleave-type semiconductor device testing apparatus is provided, which is capable of testing an IC under test in either case that the latency (the number of delay cycles) N of the IC under test is an odd number or an even number. In each of plural test circuit units (4-1 and 4-2) is provided a clock control circuit (23) comprising an adder for adding up the test period Tr of the IC tester and a clock setting value Tc, and a selector (22) for selecting the output from the adder or the clock setting value Tc to output the selected one. The latency is set in a delay setting register (5) which supplies to the selector a binary number “0” when the latency is an even number and a binary number “1” when the latency is an odd number.

Abstract: A timing generator capable of setting data indicating that a timing signal is to be generated in the next cycle, even in the case of generating test pattern signals in multiple way system is provided.

Abstract: An I/O pin electronics circuit for semiconductor test system to perform an I/O common test as well as an I/O separate device test without causing unused circuit in a comparison circuit, a comparison voltage generation circuit, a wave formatter circuit and a supply voltage generation circuit and without decreasing the number of devices that can be simultaneously tested, for high speed devices where an I/O dead band poses a problem. The I/O pin electronics circuit includes a pair of drivers which are commonly connected to a supply/termination voltage generation circuit and a wave formatter circuit, and a comparator having a comparison circuit and a comparison voltage generation circuit is connected to one of the drivers.

Abstract: A memory test system is to perform two or more comparison operations within one test cycle. The memory test system includes a pattern generator for generating test data patterns to be supplied to the memory device under test, a data selector for providing the test data patterns in a parallel fashion at a plurality of ports, a test data multiplexer for selecting one of the test data patterns at the plurality of ports to supply a plurality of test data patterns to the memory device in a series fashion within each of the predetermined test cycle, an expected value select circuit for selectively providing the test data pattern as expected value data in a parallel fashion, and a logic comparator for receiving, in a parallel fashion, an output signal from the memory device under test generated as a result of the test data patterns and comparing, in parallel, the output signals with the expected value data from the expected value select circuit.