Abstract: An information processing apparatus includes a unit to receive designation of a plurality of information acquiring targets; a unit generating second discrimination information on a basis of a plurality of pieces of first discrimination information that respectively discriminate the plurality of designated information acquiring targets; a storing unit storing a relation between the first discrimination information and the second discrimination information; and an outputting unit to output the second discrimination information.

Abstract: There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor.

Abstract: There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor.

Abstract: Logic emulation according to the present invention is aimed at an object to provide a logic dividing and module wiring system for operating logic related to external interface signals and interface signals among circuits obtained as a result of division or a logic circuit at a high speed. In a logic emulation system, information on assignments of external interface signals of logic to connector pins is read in during division of the logic. Logic related to an external interface signal assigned to a connector pin is assigned to a field programmable gate array directly connected to the connector pin. In addition, delays are checked after the division of a logic circuit in order to determine the level of delay criticality of each interface signal between field programmable gate arrays. Wiring of a module is then carried out in accordance with the levels of criticality.

Abstract: A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system.

Abstract: A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.

Abstract: A control system with an abnormality detecting device for use in a motor vehicle. The control system comprises a microcomputer coupled through a switching circuit and an analog-to-digital converter to a sensor for sensing an operating state of the motor vehicle and also to a reference voltage generating circuit. The switching circuit performs a switching operation between an analog signal from the sensor and a predetermined reference voltage signal from the reference voltage generating circuit to supply the analog-to-digital converter with one of the analog signals which is analog-to-digital-converted in the analog-to-digital converter.